Negative resistance circuit

• US 20040183628A1
• Filed: 01/28/2004
• Published: 09/23/2004
• Est. Priority Date: 01/31/2003
• Status: Active Grant

• Current Assignee: General Research of Electronics, Inc.
• Original Assignee: General Research of Electronics, Inc.
• Inventors: Kawai, Kazuo
• Granted Patent: US 6,985,053 B2
• Time in Patent Office: Days
• US Class Current: 333/217
• CPC Class Codes: H03H 11/44 Negative impedance converters H03H11/42 takes precedence; used in frequency selective networks H03H11/10

Abstract

In order to provide a negative resistance circuit which is not influenced by means of change of temperature and source voltage, etc., operates stably and has simple circuit construction, a first stage circuit of the negative resistance circuit is a collector-emitter dividing type amplifying circuit comprising of a npn transistor and a second stage circuit thereof is an emitter earth type amplifying circuit comprising of a pnp transistor. A collector output of the pnp transistor is connected to a base of the npn transistor to constitute a positive feedback path and is divided and is connected to an emitter of the npn transistor to constitute a negative feedback path.

An amplification factor A of the emitter earth type amplifying circuit and voltage dividing ratio β is set to be (1+Aβ)<A.

Claims

1. A negative resistance circuit comprising:

subtracting means to which an input signal is applied;

amplifying means for amplifying an output signal of the subtracting means;

positive feedback means for positively feeding back an output signal of the amplifying means to an input of the subtracting means;

dividing means for dividing the output signal of the amplifying mans;

negative feedback means for negatively feeding back a divided output signal of the dividing means; and

dividing ratio of the dividing means and amplification factor of the amplifying means being set to provide negative resistance between an input of the subtracting means and earth.

2. A negative resistance circuit according to claim 1 wherein the subtracting means is constituted by a collector-emitter dividing type amplifying circuit comprising of a npn transistor, and the amplifying means is constituted by an emitter earth type amplifying circuit comprising of a pnp transistor, the input signal being applied to a base of the npn transistor, a collector output thereof being connected to a base of the pnp transistor to take out it as said output signal.

3. A negative resistance circuit according to claim 1 wherein the subtracting means is constituted by a collector-emitter dividing type amplifying circuit comprising of a pnp transistor and the amplifying means is constituted by an emitter earth type amplifying circuit comprising of a npn transistor, the input signal being applied to a base of the pnp transistor, a collector output thereof being connected to a base of the npn transistor to take out it as said output signal.

4. A negative resistance circuit according to claim 1 wherein the subtracting circuit is constituted by a collector-emitter dividing type amplifying circuit comprising of a first transistor and the amplifying means is constituted by an emitter earth type amplifying circuit comprising of a second transistor, the input signal being applied to a base of the first transistor, a collector output thereof being connected capacitively to a base of the second transistor to take out it as said output signal.

5. A negative resistance circuit according to claim 1 wherein the subtracting means is constituted by a drain-source dividing type amplifying circuit comprising of a first FET transistor and the amplifying means is constituted by a source earth type amplifying circuit comprising of a second FET transistor, the input signal being applied to a gate of the first FET transistor, an output thereof being connected to a gate of the second FET transistor to take out it as said output signal.