Image processor with frame-rate conversion

• US 20040183945A1
• Filed: 03/02/2004
• Published: 09/23/2004
• Est. Priority Date: 03/06/2003
• Status: Abandoned Application

• Current Assignee: Pioneer Corporation
• Original Assignee: Pioneer Corporation
• Inventors: Matsuno, Atsushi, Nagakubo, Tetsuro, Ochiai, Kazunori
• Application Number:
  US10/790,195
• Publication Number:
  US 20040183945A1
• Time in Patent Office: Days
• US Class Current: 348/441
• CPC Class Codes: G09G 5/395 Arrangements specially adapted for transferring the contents of the bit-mapped memory to the screen G09G5/399 takes precedence
• CPC Class Codes: H04N 7/0105 using a storage device with different write and read speed

Abstract

Disclosed is an image processor with frame-rate conversion that can perform frame-rate conversion of a video signal with a single frame memory. In this image processor with frame-rate conversion, input digital video signals are successively written on the frame memory with a timing synchronized with a vertical synchronization signal included in the input digital video signals. During this time, a frequency signal that mainly consists of a train of N pulses for every M cycles of the vertical synchronization signal is generated as a vertical synchronization signal being rate-converted, and the input digital video signals stored in the frame memory are read out in the order in which they were written with a timing synchronized with the vertical synchronization signal being rate-converted. Such a configuration makes it possible to convert the input digital video signals to video signals having a desired vertical synchronization frequency with use of a single frame memory, thereby converting frame-rate.

Claims

1. An image processor with frame-rate conversion that generates video signals being rate-converted by converting a vertical synchronization frequency of input digital video signals consisting of successive frames into a desired frequency, said image processor comprising:

a frame memory having a storage capacity for a single frame of said input digital video signals;

a memory write control circuit which successively writes said input digital video signals on said frame memory with a timing synchronized with a vertical synchronization signal included in said input digital video signals;

a vertical synchronization signal generating circuit which produces a frequency signal mainly consisting of a train of N pulses (N being a natural number) for every M cycles (M being a natural number) of the vertical synchronization signal, as a vertical synchronization signal being rate-converted, the natural number N being larger than the natural number M; and

a memory readout control circuit which reads out and outputs the input digital video signals from said frame memory in the order in which said input digital video signals were written and with a timing synchronized with the vertical synchronization signal being rate-converted, as said video signals being rate-converted.

2. An image processor with frame-rate conversion according to claim 1, wherein the natural number N is smaller than two times the natural number M.