Semiconductor memory and method for controlling the same

• US 20040184325A1
• Filed: 09/05/2003
• Published: 09/23/2004
• Est. Priority Date: 09/13/2002
• Status: Active Grant

• Current Assignee: Fujitsu Semiconductor Limited (Fujitsu Limited)
• Original Assignee: Fujitsu Limited
• Inventors: Fujioka, Shinya, Sato, Kotoku, Yamada, Shinichi, Ohno, Jun
• Granted Patent: US 6,842,391 B2
• Time in Patent Office: Days
• US Class Current: 365/191
• CPC Class Codes: G11C 2207/2227 Standby or low power modes
• CPC Class Codes: G11C 7/1018 Serial bit line access mode, e.g. using bit line address shift registers, bit line address counters, bit line burst counters
• CPC Class Codes: G11C 7/22 Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management

Abstract

A method for controlling a semiconductor memory in which mode register can be set in burst mode. To set an operation mode in burst mode, the semiconductor memory is changed first from the burst mode, through power-down mode, to standby mode of non-burst mode. Then the semiconductor memory is changed to mode register set mode to set the mode register when commands are input in the same predetermined sequence that is used in the non-burst mode.

Claims

1. A method for controlling a semiconductor memory, the method comprising the steps of:

changing the semiconductor memory from burst mode, through power-down mode, to standby mode of non-burst mode in the case of setting a mode register for setting an operation mode in the burst mode;

changing the semiconductor memory from the standby mode of the non-burst mode to mode register set mode in the case of commands being input in predetermined sequence in the standby mode of the non-burst mode; and

setting the mode register according to input from outside.

2. The method for controlling a semiconductor memory according to claim 1, wherein the mode register includes a bit for prohibiting resetting, further wherein the contents of the mode register are not reset in the power-down mode if the bit has been set.

3. The method for controlling a semiconductor memory according to claim 1, wherein the predetermined sequence includes a set of six commands of one read command combined with the most significant bit of an address, four write commands each combined with the most significant bit of the address, and the one read command combined with the address indicative of the operation mode.

4. A semiconductor memory comprising:

a mode setting control circuit with a mode register to set an operation mode for setting the mode register in the case of commands being input in predetermined sequence in standby mode of non-burst mode; and

a power-down control circuit for changing the semiconductor memory from standby mode of burst mode, through power-down mode, to the standby mode of the non-burst mode.

5. The semiconductor memory according to claim 4, wherein the mode register includes a bit for prohibiting resetting, further wherein the contents of the mode register are not reset in the power-down mode if the bit has been set.

6. The semiconductor memory according to claim 4, wherein the predetermined sequence includes a set of six commands of one read command combined with the most significant bit of an address, four write commands each combined with the most significant bit of the address, and the one read command combined with the address indicative of the operation mode.