Semiconductor wafer, semiconductor chip, and manufacturing method of semiconductor device

• US 20040184344A1
• Filed: 01/27/2004
• Published: 09/23/2004
• Est. Priority Date: 07/19/2000
• Status: Active Grant

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: Sadayuki Morita, Takahiro Sonoda, Yoshikazu Saitoh
• Inventors: Saitoh, Yoshikazu, Sonoda, Takahiro, Morita, Sadayuki
• Granted Patent: US 6,885,599 B2
• Time in Patent Office: Days
• US Class Current: 365/233
• CPC Class Codes: G11C 29/48 Arrangements in static stores specially adapted for testing by means external to the store, e.g. using direct memory access [DMA] or using auxiliary access paths

Abstract

By using a small number of needles and contact terminals at burn-in, electric contact check is performed between each needle and each terminal provided in each semiconductor chip, and thereby the yield of assembled products can be improved. A packaging structure in which, for example, a volatile memory chip and a nonvolatile memory chip are formed is assembled in accordance with a production scheme in which burn-in of each memory chip is performed while still under the state of a semiconductor wafer, and by forming the packaged structure using the good volatile memory chip subjected to burn-in and likewise, also, the nonvolatile memory chip. At this burn-in, contact check is performed by bringing a needle, provided in a burn-in board, into contact with, for example, six test-only signal terminals of a test circuit formed on each semiconductor chip.

Claims

1. A semiconductor wafer including a plurality of semiconductor chip areas, each of which includes a memory matrix, characterized in that

said each of the semiconductor chips contains a first terminal and a second terminal, the first terminal inputting a signal for judging electric connection/non-connection between a needle connected to a test apparatus at burn-in and a terminal provided in each of the semiconductor chips, and the second terminal outputting a response signal for responding to this input signal.

2. A semiconductor wafer including a plurality of semiconductor chip areas, each of which includes a memory matrix, characterized in that

said each of the semiconductor chips contains a plurality of address input terminals for specifying an address of said memory matrix;

a plurality of data input/output terminals for inputting and outputting write data and read data;

a plurality of control signal terminals for controlling write and read operations; and

a plurality of test-only signal terminals for judging electric connection/non-connection between a needle connected to a test apparatus at burn-in and a terminal provided in each of the semiconductor chips.

3. A semiconductor chip comprising:

a memory circuit containing a memory matrix; and

a test circuit inputting a signal for judging electric connection/non-connection between a needle connected to a test apparatus at burn-in and a terminal of a semiconductor chip, and outputting a response signal for responding to this input signal, and judging electric connection/non-connection between a needle connected to said test apparatus at said burn-in and a terminal of said semiconductor chip.

4. The semiconductor chip according to claim 3, wherein said test circuit comprises:

a test clock terminal for inputting a test clock signal;

a first and second test control terminals for inputting a test control signal;

a test input/output terminal for inputting and outputting test input/output data;

a first power terminal supplying with a first power supply voltage; and

a second power terminal supplying with a second power supply voltage.

5. A manufacturing method of semiconductor device in which semiconductor chips are cut out from a semiconductor wafer and a first semiconductor chip and a second semiconductor chip, separated from each other, are formed,

the method comprising a step of performing burn-in of said first and second semiconductor chips before the semiconductor chips are cut out from said semiconductor wafer.

6. The manufacturing method of semiconductor device according to claim 5, wherein said step of performing burn-in contains a step of performing a contact check for judging electric connection/non-connection between each needle connected to a test apparatus and each terminal provided in each of said first and second semiconductor chips of said semiconductor wafer.

7. The manufacturing method of semiconductor device according to claim 6, wherein said first and second semiconductor chips are cut out from semiconductor wafers different from each other.

8. The manufacturing method of semiconductor device according to claim 5, wherein said first and second semiconductor chips are cut out from semiconductor wafers different from each other.