Quadra-polar modulator

• US 20040184559A1
• Filed: 03/18/2003
• Published: 09/23/2004
• Est. Priority Date: 03/18/2003
• Status: Active Grant

• Current Assignee: Qualcomm, Inc.
• Original Assignee: Qualcomm, Inc.
• Inventors: Ballantyne, Gary J.
• Granted Patent: US 6,983,024 B2
• Time in Patent Office: Days
• US Class Current: 375/300
• CPC Class Codes: H03C 1/547 using field-effect transistors
• CPC Class Codes: H03F 3/2176 Class E amplifiers
• CPC Class Codes: H04L 27/362 Modulation using more than one carrier, e.g. with quadrature carriers, separately amplitude modulated H04L27/366 takes precedence

Abstract

A quadra-polar modulator that is simple to implement and also provides good noise performance. The quadra-polar modulator includes four amplitude modulators and a combiner. Each amplitude modulator modulates a respective carrier signal with a respective input signal to provide a respective output signal. The combiner then combines the four output signals from the four amplitude modulators to provide a modulated signal. Each amplitude modulator may be implemented with a switching amplifier, such as a supply modulated class E amplifier. Two input signals are obtained by summing separately an inphase (I) modulating signal and an inverted I modulating signal with an offset value. The other two input signals are obtained by summing separately a quadrature (Q) modulating signal and an inverted Q modulating signal with the offset value. The offset value can be selected based on the expected magnitude of the modulating signals. The four carrier signals are in quadrature to each other.

Claims

1. An integrated circuit comprising:

a first amplitude modulator operative to modulate a first carrier signal with a first input signal to provide a first output signal;

a second amplitude modulator operative to modulate a second carrier signal with a second input signal to provide a second output signal, wherein the first and second input signals are derived based on a first modulating signal;

a third amplitude modulator operative to modulate a third carrier signal with a third input signal to provide a third output signal;

a fourth amplitude modulator operative to modulate a fourth carrier signal with a fourth input signal to provide a fourth output signal, wherein the third and fourth input signals are derived based on a second modulating signal; and

a combiner operative to combine the first, second, third, and fourth output signals to provide a modulated signal.

2. The integrated circuit of claim 1, further comprising:

a first summer operative to sum the first modulating signal with an offset value to provide the first input signal;

a second summer operative to sum an inverted version of the first modulating signal with the offset value to provide the second input signal;

a third summer operative to sum the second modulating signal with the offset value to provide the third input signal; and

a fourth summer operative to sum an inverted version of the second modulating signal with the offset value to provide the fourth input signal.

3. The integrated circuit of claim 2, wherein the offset value is selected based on expected magnitude of the first and second modulating signals.

4. The integrated circuit of claim 3, wherein the offset value is a fixed value.

5. The integrated circuit of claim 3, wherein the offset value is a variable value.

6. The integrated circuit of claim 1, wherein the first, second, third, and fourth amplitude modulators are switching amplifiers.

7. The integrated circuit of claim 1, wherein each of the first, second, third, and fourth amplitude modulators is implemented with a supply modulated class E, class D, class F, class inverse-F, or class E/F_odd amplifier.

8. The integrated circuit of claim 1, further comprising:

a quadrature splitter operative to receive a local oscillator (LO) signal and provide the first, second, third, and fourth carrier signals.

9. The integrated circuit of claim 1, wherein the first, second, third, and fourth carrier signals are 90 degrees out of phase of each other.

10. The integrated circuit of claim 1, wherein the first, second, third, and fourth amplitude modulators are implemented in complementary metal oxide semiconductor (CMOS).

11. The integrated circuit of claim 1, wherein the modulated signal is a CDMA signal.

12. The integrated circuit of claim 1, wherein the modulated signal is a GSM signal.

13. A device comprising:

a quadrature splitter operative to receive a local oscillator (LO) signal and provide first, second, third, and fourth carrier signals; and

a quadra-polar modulator operative to receive and amplitude modulate the first, second, third, and fourth carrier signals with first and second modulating signals to provide a modulated signal.

14. The device of claim 13, wherein the quadra-polar modulator includes

a first amplitude modulator operative to modulate the first carrier signal with a first input signal to provide a first output signal,

a second amplitude modulator operative to modulate a second carrier signal with a second input signal to provide a second output signal, wherein the first and second input signals are derived based on the first modulating signal,

a third amplitude modulator operative to modulate a third carrier signal with a third input signal to provide a third output signal,

a fourth amplitude modulator operative to modulate a fourth carrier signal with a fourth input signal to provide a fourth output signal, wherein the third and fourth input signals are derived based on the second modulating signal, and

a combiner operative to combine the first, second, third, and fourth output signals to provide the modulated signal.

15. The device of claim 14, wherein the first, second, third, and fourth amplitude modulators are switching amplifiers.

16. The device of claim 14, wherein the first, second, third, and fourth input signals are derived based on the first and second modulating signals and an offset value, and wherein the offset value is selected based on expected magnitude of the first and second modulating signals.

17. The device of claim 13, wherein the modulated signal is a CDMA signal.

18. An apparatus comprising:

means for amplitude modulating a first carrier signal with a first input signal to provide a first output signal;

means for amplitude modulating a second carrier signal with a second input signal to provide a second output signal, wherein the first and second input signals are derived based on a first modulating signal;

means for amplitude modulating a third carrier signal with a third input signal to provide a third output signal;

means for amplitude modulating a fourth carrier signal with a fourth input signal to provide a fourth output signal, wherein the third and fourth input signals are derived based on a second modulating signal; and

means for combining the first, second, third, and fourth output signals to provide a modulated signal.

19. The apparatus of claim 18, further comprising:

means for summing the first modulating signal with an offset value to provide the first input signal;

means for summing an inverted version of the first modulating signal with the offset value to provide the second input signal;

means for summing the second modulating signal with the offset value to provide the third input signal; and

means for summing an inverted version of the second modulating signal with the offset value to provide the fourth input signal.

20. The apparatus of claim 18, wherein the modulated signal is a CDMA signal.

21. A method of performing modulation in a wireless communication system, comprising:

amplitude modulating a first carrier signal with a first input signal to provide a first output signal;

amplitude modulating a second carrier signal with a second input signal to provide a second output signal, wherein the first and second input signals are derived based on a first modulating signal;

amplitude modulating a third carrier signal with a third input signal to provide a third output signal;

amplitude modulating a fourth carrier signal with a fourth input signal to provide a fourth output signal, wherein the third and fourth input signals are derived based on a second modulating signal; and

combining the first, second, third, and fourth output signals to provide a modulated signal.