Timing synchronization for M-DPSK channels

• US 20040184564A1
• Filed: 03/19/2003
• Published: 09/23/2004
• Est. Priority Date: 03/19/2003
• Status: Active Grant

• Current Assignee: Apple Inc.
• Original Assignee: Freescale Semiconductor, Inc. (NXP Semiconductors NV)
• Inventors: Chen, Weizhong, Dehner, Leo
• Granted Patent: US 6,973,142 B2
• Time in Patent Office: Days
• US Class Current: 375/330
• CPC Class Codes: H04L 27/22 Demodulator circuits; Receiver circuits
• CPC Class Codes: H04L 7/042 Detectors therefor, e.g. correlators, state machines digital correlators in general G06F17/15

Abstract

The present invention discloses an improved method of timing synchronization with transmitted data packets in a receiver on a communication channel using differential phase shift keying (DPSK) modulation—especially an RF wireless communication channel. The invention reduces the complexity of the circuits, especially the multipliers, required for digital signal processing. The invention also increases performance compared to previously known methods.

Claims

1. A differential phase shift signal receiver comprising:

a demodulator comprising a first input to receive a digital phase shift signal, and an output to provide a digital phase shift base-band signal;

an analog to digital sampling module comprising an input coupled to the output of the demodulator, and an output to provide a sampled digital phase shift base-band signal; and

a synchronization detection module comprising an input coupled to the output of the demodulator, a first output to provide a symbol center sample index that identifies a sample of the sampled digital phase shift base-band signal having a predefined relationship to a center of a received symbol, and a second output to provide a sample interval fraction that identifies a fractional portion of a sample period from the sample identified by the symbol center sample index to an estimated center of the received symbol.

2. The receiver of claim 1, wherein the predefined relationship of the sample to the center of the received center identifies the sample immediately before the center of the received symbol.

3. The receiver of claim 2, wherein the received symbol is a portion of a synchronization pattern.

4. The receiver of claim 1, wherein the received symbol is a portion of a synchronization pattern.

5. The receiver of claim 1, wherein the synchronization detection module comprises:

a phase differential detection module to receive the sampled digital phase shift base-band signal and to produce a sequence of phase differential samples;

a signal correlation module responsive to the phase differential detection module, the signal correlation module including a sample correlation module, the sample correlation module having a first input to receive the sequence of phase differential samples and a second input to receive a predetermined synchronization symbol pattern, the predetermined synchronization symbol pattern associated with the predetermined synchronization bit pattern, the sample correlation module to produce symbol correlation values; and

a timing detection module responsive to the signal correlation module to generate the symbol center sample index and the sample interval fraction.

6. The receiver of claim 5, wherein the synchronization module further comprises:

a bit correlation module responsive to the phase differential detection module, the bit correlation module including a bit recovery module responsive to the sequence of phase differential samples and producing a recovered candidate bit stream, the bit correlation module including a binary correlation module, the binary correlation module having a first input to receive the recovered candidate bit stream and a second input to receive a predetermined synchronization bit pattern, the binary correlation module to produce bit correlation values; and

the timing detection module further responsive to the bit correlation module.

7. The receiver of claim 6, wherein the timing detection logic module includes a data packet detection module to detect arrival of a data packet based on a comparison of the bit correlation values.

8. The receiver of claim 6, further comprising a peak tuning module to determine the sample interval fraction value using polynomial estimation.

9. The receiver of claim 8, wherein the polynomial estimation utilizes an estimated maximum value of a non-linear polynomial matched to the symbol correlation values.

10. The receiver of claim 6, wherein the phase differential phase shift keying signal is derived from a received wireless signal.

11. The receiver of claim 10, wherein the wireless signal is a Bluetooth standard compliant signal.

12. The receiver of claim 6, wherein the signal correlation module performs multiplication of a multi-bit value associated with at least one of the phase differential samples with a 1-bit value associated with at least one sample of the predetermined synchronization symbol pattern.

13. The receiver of claim 6, wherein the sample correlation module performs a correlation on a selected subset of the phase differential samples.

14. The receiver of claim 13, wherein the selected subset includes every fourth phase differential sample from the sequence of phase differential samples.

15. The receiver of claim 6, wherein the predetermined synchronization bit pattern is the same as the predetermined synchronization symbol pattern.

16. A differential phase shift signal receiver comprising:

a phase differential detection module to receive a differential phase shift keying signal and to produce a sequence of phase differential samples;

a bit correlation module responsive to the phase differential detection module, the bit correlation module including a bit recovery module responsive to the sequence of phase differential samples and producing a recovered candidate bit stream, the bit correlation module including a binary correlation module, the binary correlation module having a first input to receive the recovered candidate bit stream and a second input to receive a predetermined synchronization bit pattern, the binary correlation module to produce bit correlation values;

a signal correlation module responsive to the phase differential detection module, the signal correlation module including a sample correlation module, the sample correlation module having a first input to receive the sequence of phase differential samples and a second input to receive a predetermined synchronization symbol pattern wherein the sample correlation module performs a correlation on a selected subset of the phase differential samples, the signal correlation module to produce signal correlation values; and

a timing detection logic module responsive to the bit correlation module and responsive to the signal correlation module, the timing detection logic module generating a synchronization indicator based on the bit correlation values and the signal correlation values.

17. A method of synchronizing a received differential phase shift signal, the method comprising:

receiving a differential phase shift keying signal;

demodulating the differential phase shift keying signal to produce a baseband differential phase shift keying signal;

determining a sequence of phase differential samples derived from the baseband differential phase shift keying signal;

recovering a candidate bit stream from the sequence of phase differential samples;

correlating the candidate bit stream with a predetermined synchronization bit pattern to produce bit stream correlation values;

correlating the sequence of phase differential samples at a symbol separation with a predetermined synchronization symbol pattern to produce signal correlation values;

comparing the bit stream correlation values with a threshold to detect a data packet;

performing peak tuning of the detected data packet to determine a sample interval fraction based on the signal correlation values; and

determining synchronization timing with respect to a start time of the detected data packet based on the detected data packet and the sample interval fraction.

18. The method of claim 17, wherein a subset of phase differential samples within a set of the phase differential samples is used during correlation with the predetermined synchronization symbol.

19. The method of claim 18, wherein the subset includes every fourth sample of the set of the phase differential samples.

20. The method of claim 17, further comprising detecting a data packet based on a comparison of the bit correlation values.

21. The method of claim 17, further comprising determining the sample interval fraction using polynomial estimation.

22. The method of claim 21, wherein the polynomial estimation further includes utilizing an estimated maximum value of a non-linear polynomial matched to the signal correlation values.

23. The method of claim 17, wherein the phase differential phase shift keying signal is a received Bluetooth standard compliant signal.

24. The method of claim 17, wherein correlating the sequence of phase differential samples with the predetermined synchronization symbol pattern comprises performing multiplication of a multibit value associated with at least one of the phase differential samples with a 1-bit value of the predetermined synchronization symbol pattern.

25. The method of claim 17, wherein the predetermined synchronization bit pattern is the same as the predetermined synchronization signal pattern.