System-on-chip (SOC) solutions with multiple devices by multiple poly gate trimming process
First Claim
1. A method of forming gate electrode layer portions having differing widths, comprising the steps of:
- a) providing a structure having two or more active areas;
b) forming a gate electrode layer over the structure;
c) forming a hard mask layer over the gate electrode layer;
d) patterning the hard mask layer within the two or more active areas to form two or more respective hard mask layer portions within the two or more active areas;
the two or more respective hard mask layer portions having a first width;
e) selectively trimming at least one of the two or more respective hard mask layer portions to reduce the width of the trimmed at least one of the two or more respective hard mask layer portions to a second width; and
f) patterning the gate electrode layer. to form respective two or more gate electrode layer portions wherein at least one of the two or more gate electrode layer portions has a second width less than at least one other of the two or more gate electrode layer portions.
1 Assignment
0 Petitions
Accused Products
Abstract
A method of forming gate electrode layer portions having differing widths comprising the following steps. A structure having a gate electrode layer and a hard mask layer thereover and including two or more active areas is provided. The hard mask layer is patterned to form two or more respective hard mask layer portions within the two or more active areas. One or more of the two or more respective hard mask layer portions is/are selectively trimmed to reduce its/their width to a second width leaving at least one the respective hard mask layer portions untrimmed. The gate electrode layer is then patterned.
-
Citations
43 Claims
-
1. A method of forming gate electrode layer portions having differing widths, comprising the steps of:
-
a) providing a structure having two or more active areas;
b) forming a gate electrode layer over the structure;
c) forming a hard mask layer over the gate electrode layer;
d) patterning the hard mask layer within the two or more active areas to form two or more respective hard mask layer portions within the two or more active areas;
the two or more respective hard mask layer portions having a first width;
e) selectively trimming at least one of the two or more respective hard mask layer portions to reduce the width of the trimmed at least one of the two or more respective hard mask layer portions to a second width; and
f) patterning the gate electrode layer.to form respective two or more gate electrode layer portions wherein at least one of the two or more gate electrode layer portions has a second width less than at least one other of the two or more gate electrode layer portions. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16)
-
-
17. A method of forming gate electrode layer portions having differing widths, comprising the steps of:
-
a) providing a structure having two or more active areas;
b) forming a gate electrode layer over the structure;
c) forming a hard mask layer over the gate electrode layer;
d) patterning the hard mask layer within the two or more active areas to form two or more respective hard mask layer portions within the two or more active areas;
the two or more respective hard mask layer portions having a first width;
e) masking one or more of the two or more respective hard mask layer portions leaving at least one of the two or more respective hard mask layer portions unmasked;
f) trimming the unmasked at least one of the two or more respective hard mask layer portions to reduce the width of the trimmed unmasked at least one of the two or more respective hard mask layer portions to a second width;
g) unmasking the masked one or more of the two or more respective hard mask layer portions; and
h) patterning the gate electrode layer using;
the unmasked one or more of the two or more respective hard mask layer portions; and
the trimmed at least one of the two or more respective hard mask layer portions as masks;
to form respective two or more gate electrode layer portions wherein at least one of the two or more gate electrode layer portions has a second width less than at least one other of the two or more gate electrode layer portions. - View Dependent Claims (18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30)
-
-
31. A method of forming gate electrode layer portions having differing widths, comprising the steps of:
-
a) providing a structure having two or more active areas;
b) forming a gate electrode layer over the structure;
c) forming a hard mask layer over the gate electrode layer;
d) patterning the hard mask layer within the two or more active areas using a patterned masking layer to form two or more respective hard mask layer portions within the two or more active areas;
the two or more respective hard mask layer portions having a first width;
e) masking one or more of the two or more respective hard mask layer portions leaving at least one of the two or more respective hard mask layer portions unmasked;
f) trimming the unmasked at least one of the two or more respective hard mask layer portions to reduce the width of the trimmed unmasked at least one of the two or more respective hard mask layer portions to a second width;
g) unmasking the masked one or more of the two or more respective hard mask layer portions; and
h) patterning the gate electrode layer using;
the unmasked one or more of the two or more respective hard mask layer portions; and
the trimmed at least one of the two or more respective hard mask layer portions as masks;
to form respective two or more gate electrode layer portions wherein at least one of the two or more gate electrode layer portions has a second width less than at least one other of the two or more gate electrode layer portions. - View Dependent Claims (32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43)
-
Specification