System and method of synthesizing a plurality of voices

• US 20040186709A1
• Filed: 03/17/2003
• Published: 09/23/2004
• Est. Priority Date: 03/17/2003
• Status: Abandoned Application

• Current Assignee: Winbond Electronics Corporation
• Original Assignee: Winbond Electronics Corporation
• Inventors: Chi, Chao-Wen
• Application Number:
  US10/390,356
• Publication Number:
  US 20040186709A1
• Time in Patent Office: Days
• US Class Current: 704/211
• CPC Class Codes: G10L 13/047 Architecture of speech synthesisers

Abstract

A system and method of synthesizing a plurality of voices are described. The system has a processing unit, a register, a latch unit, a timer and a digital/analog converter. The processing unit decodes voice data into decoded voices and the decoded voices are then transmitted to the register. A plurality of different sampling signals of the timer are transmitted to the latch unit to trigger periodically the latch unit and the latch unit sequentially fetches the decoded voices stored in the register to prevent effectively jitters when the voice data are synthesized.

Claims

1. A system of synthesizing a plurality of voices by calculating voice data to generate a synthesized voice to prevent jitters in the synthesized voice, the system comprising:

a memory for storing the voice data;

a processing unit coupled to the memory and triggered by a clock signal so that the processing unit can read the voice data stored in the memory and decode the voice data into a decoded voice;

a register coupled to the processing unit and actuated by the clock signal for receiving the decoded voice from the processing unit;

a latch unit coupled to the register and controlled by a timer for acquiring the decoded voices within the register, wherein the timer transmits a sampling signal to the latch unit for triggering periodically the latch unit according to a period of the sampling signal and the latch unit sequentially reads the decoded voices from the processing unit to prevent jitters in the synthesized voice; and

a digital/analog converter coupled to the latch unit for transferring the decoded voice into an analog synthesized voice to output the analog synthesized voice.

2. The system of claim 1, wherein the latch comprises a plurality of layers of depth for storing the decoded voice from the processing unit.

3. The system of claim 2, wherein the latch comprises a random access memory (RAM).

4. The system of claim 2, wherein the layers of depth comprise a FIFO method of transferring the decoded voice from the processing unit to the latch unit.

5. The system of claim 1, wherein the processing unit comprises a micro-controller or a central processing unit (CPU).

6. The system of claim 1, wherein the processing unit comprises a waveform coding method for coding the voice data in the memory.

7. The system of claim 6, wherein the waveform coding method comprises code excited linear prediction (CELP).

8. The system of claim 6, wherein the waveform coding method comprises adaptive differential pulse code modulation (ADPCM).

9. The system of claim 6, wherein the waveform coding method comprises differential pulse code modulation (DPCM).

10. A system of synthesizing a plurality of voices by calculating voice data in memory to generate a synthesized voice to prevent jitters in the synthesized voice, the system comprising:

a processing unit coupled to the memory and triggered by a clock signal, wherein the processing unit reads the voice data stored in the memory and decode the voice data into a decoded voice;

a register coupled to the processing unit and actuated by the clock signal for receiving the decoded voice from the processing unit;

a latch unit coupled to the register and controlled by a plurality of timers for acquiring the decoded voices within the register, wherein the timers transmit a plurality of sampling signals responsive to the timers to the latch unit for triggering periodically the latch unit according to the different period of each of the sampling signals and the latch unit sequentially reads the decoded voices from the processing unit to prevent jitters in the synthesized voice; and

a digital/analog converter coupled to the latch unit for transferring the decoded voice into an analog synthesized voice and to output the analog synthesized voice.

11. The system of claim 10, wherein the latch comprises a plurality of layers of depth for storing the decoded voice from the processing unit.

12. The system of claim 11, wherein the layers of depth comprises a FIFO method of transferring the decoded voice from the processing unit to the latch unit.

13. The system of claim 10, wherein the processing unit comprises a micro-controller or a central processing unit (CPU).

14. The system of claim 10, wherein the processing unit comprises a waveform coding method for coding the voice data in the memory.

15. The system of claim 14, wherein the waveform coding method comprises code excited linear prediction (CELP).

16. The system of claim 14, wherein the waveform coding method comprises adaptive differential pulse code modulation (ADPCM).

17. The system of claim 14, wherein the waveform coding method comprises differential pulse code modulation (DPCM).

18. A method of synthesizing a plurality of voices by calculating voice data in memory to generate a synthesized voice to prevent jitters in the synthesized voice, the method comprising the steps of:

reading the voice data stored in the memory by using a processing unit according to a clock signal;

decoding the voice data to into a decoded voice by the processing unit;

triggering a register with the clock signal to receive the decoded voice from the processing unit;

controlling a latch unit by generating a plurality of sampling signals responsive to a plurality of timers, wherein the timers transmit a plurality of sampling signals responsive to the timers to the latch unit for triggering periodically the latch unit according the different periods of each of the sampling signals and the latch unit sequentially reads the decoded voices from the processing unit to prevent jitters in the synthesized voice;

transforming the digital decoded voice into an analog decoded voice; and

outputting the analog decoded voice.

19. The system of claim 18, wherein the register comprises a plurality of layers of depth for storing the decoded voice from the processing unit.

20. The system of claim 19, wherein the layers of depth comprise a FIFO method of transferring the decoded voice from the processing unit to the latch unit.

21. The system of claim 18, wherein the processing unit comprises a micro-controller or a central processing unit (CPU).

22. The system of claim 18, wherein the processing unit comprises a waveform coding method for coding the voice data in the memory.

23. The system of claim 22 wherein the waveform coding method comprises code excited linear prediction (CELP).

24. The system of claim 22, wherein the waveform coding method comprises adaptive differential pulse code modulation (ADPCM).

25. The system of claim 22, wherein the waveform coding method comprises differential pulse code modulation (DPCM).