Subsystem boot and peripheral data transfer architecture for a subsystem of a system-on- chip
First Claim
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1. In a subsystem of a system, a method comprising:
- a Direct Memory Access (DMA) device of the subsystem detecting a subsystem reset state;
in response, the DMA device awaits notification by a data transfer unit of the subsystem, of receipt of a data packet addressed to the DMA device;
retrieving from said data transfer unit said received data packet, by said DMA device, and extracting from said retrieved data packet, location information identifying storage locations external to said subsystem where boot code of said subsystem are stored;
accessing said external storage locations through said data transfer unit, by said DMA device, and transferring said boot code into a memory unit of said subsystem; and
interrupting a processor of said subsystem by said DMA device to transfer control to said processor to execute said boot code to start up said subsystem.
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Abstract
A subsystem (200) is provided at least Direct Memory Access (DMA) device (220) utilized to provide instructions to facilitate the operation of a substem processor (210). In one embodiment, a system level processor (102) initiates the provision of instructions for a subsystem (210). The DMA device may be additionally or alternatively utilized to provide data transfer capabilities to a plurality of data channels in a subsytem (200). The DMA device processes channels in a time limited manner to ensure that data is porcessed in a manner appropriate for time critical data.
60 Citations
52 Claims
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1. In a subsystem of a system, a method comprising:
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a Direct Memory Access (DMA) device of the subsystem detecting a subsystem reset state;
in response, the DMA device awaits notification by a data transfer unit of the subsystem, of receipt of a data packet addressed to the DMA device;
retrieving from said data transfer unit said received data packet, by said DMA device, and extracting from said retrieved data packet, location information identifying storage locations external to said subsystem where boot code of said subsystem are stored;
accessing said external storage locations through said data transfer unit, by said DMA device, and transferring said boot code into a memory unit of said subsystem; and
interrupting a processor of said subsystem by said DMA device to transfer control to said processor to execute said boot code to start up said subsystem. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
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11. A subsystem of a system comprising:
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a processor;
a data transfer unit;
a Direct Memory Access (DMA) device to detect a subsystem reset state where, in response to said detection, said DMA device awaits notification by said data transfer unit of receipt of a data packet addressed to said DMA device and where said DMA device retrieves from said data transfer unit said received data packet and extracts from said retrieved data packet location information identifying storage locations external to said subsystem where boot code of said subsystem is stored and where said DMA accesses said external storage locations through said data transfer unit and transfers said boot code into a memory unit of said subsystem and said DMA interrupts said processor of said subsystem to transfer control to said processor to execute said boot code to start up said subsystem. - View Dependent Claims (12, 13, 14, 15, 16, 17, 18, 19, 20)
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21. A subsystem of a system comprising:
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at least one memory unit;
an I/O interface coupling a first and a second peripheral device to said subsystem;
a DMA engine coupled to said memory unit and said I/O interface to correspondingly transfer first and second data between said at least one memory unit and said first and second peripheral devices in an interleaved manner, said first and second data having first and second plurality of data segments respectively, and the DMA engine including a) a plurality of registers to collectively store a selected one of a first and a second descriptor correspondingly describing said first and second plurality of data segments of said first and second data; and
b) a control portion coupled to said registers to cause said first descriptor to be loaded into said registers at a first point in time, a first subset of said first data to be transferred in accordance with said loaded first descriptor, said first descriptor to be updated and saved, said second descriptor to be loaded into said registers at a second point in time, and a second subset of said second data to be transferred in accordance with said second descriptor. - View Dependent Claims (22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36)
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37. In a subsystem of a system, a method of correspondingly transferring first and second data between at least one memory unit and first and second peripheral devices in an interleaved manner comprising:
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loading a first descriptor into a plurality of registers at a first point in time, said first descriptor describing a first plurality of data segments of said first data;
transferring a first subset of said first data in accordance with said first descriptor;
updating said first descriptor;
saving said first descriptor; and
loading a second descriptor into said plurality of registers at a second point in time, said second descriptor describing a second plurality of data segments of said second data. - View Dependent Claims (38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51, 52)
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Specification