Method and apparatus for communications interfacing capable of effectively reducing disk drive power consumption
First Claim
1. A communications interface apparatus, comprising:
- a register circuit storing data to be transferred to a host computer;
a first memory storing first information indicating a specific address of the register circuit and representing an access to the communications interface apparatus executed by the host computer for a data transfer;
a second memory storing second information, sent from the host computer in association with the first information stored in the first memory, to be written into the register circuit at the specific address indicated by the first information stored in the first memory; and
a control circuit configured to perform an information writing operation for writing the first information into the first memory and the second information into the second memory in chronological order of accesses executed.
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Accused Products
Abstract
A communications interface apparatus includes a register, first and second memories, and a control circuit. The register circuit stores data to be transferred to a host computer. The first memory stores first information indicating a specific address of the register and representing an access to the apparatus executed by the host computer for a data transfer. The second memory stores second information, sent from the host computer in association with the first information stored in the first memory, to be written into the register at the specific address indicated by the first information stored in the first memory. The control circuit performs an information writing operation for writing the first information into the first memory and the second information into the second memory in chronological order of accesses executed.
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Citations
19 Claims
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1. A communications interface apparatus, comprising:
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a register circuit storing data to be transferred to a host computer;
a first memory storing first information indicating a specific address of the register circuit and representing an access to the communications interface apparatus executed by the host computer for a data transfer;
a second memory storing second information, sent from the host computer in association with the first information stored in the first memory, to be written into the register circuit at the specific address indicated by the first information stored in the first memory; and
a control circuit configured to perform an information writing operation for writing the first information into the first memory and the second information into the second memory in chronological order of accesses executed. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9)
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10. A communications interfacing method comprising the steps of:
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storing in a register circuit data to be transferred to a host computer;
storing in a first memory first information indicating a specific address of the register circuit and representing an access to a communications interface apparatus executed by the host computer for a data transfer, and storing in a second memory second information, sent from the host computer in association with the first information stored in the first memory, to be written into the register circuit at the specific address indicated by the first information stored in the first memory; and
performing an information writing operation with a control circuit for writing the first information into the first memory and the second information into the second memory in chronological order of accesses executed. - View Dependent Claims (11, 12, 13, 14, 15, 16, 17, 18)
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19. An optical disk drive apparatus, comprising:
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an optical disk drive mechanism; and
an interface circuit for interfacing communications, between the optical disk drive mechanism and a host computer, the interfacing circuit comprising;
an input terminal for receiving data sent from the host computer;
a data processor configured to perform a predetermined data processing operation to the data received through the input terminal;
a clock generator configured to generate a clock signal with which the data processor performs the predetermined data processing operation;
an operation mode changer configured to control the clock generator to reduce a frequency of the clock signal to a value smaller than a predetermined value to change an operation mode from a regular operation mode to a low power consumption mode;
a buffering circuit block configured to buffer the data received through the input terminal, the buffering circuit block including;
a first data transfer path configured to transfer the data received through the input terminal to the data processor not via a memory, and a second data transfer path configured to transfer the data received through the input terminal to the data processor via a memory; and
a path selection controller configured to control the buffering circuit clock to select the second data transfer path on an exclusive basis when the operation mode is changed from the regular operation mode to the low power consumption mode.
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Specification