Configurable width buffered module
First Claim
1. A memory module comprising:
- a connector interface which includes a first contact and a second contact;
a first integrated circuit having memory including a first storage cell and a second storage cell; and
a buffer device coupled to the first integrated circuit and the connector interface, wherein the buffer device is operable in a first mode and a second mode, wherein;
during the first mode of operation, the first storage cell and the second storage cell are accessible from the first contact; and
during the second mode of operation, the first storage cell is accessible from the first contact and the second storage cell is accessible from the second contact.
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Accused Products
Abstract
A memory system architecture/interconnect topology includes a configurable width buffered module having a configurable width buffer device. The configurable width buffer device is coupled to at least one memory device on the configurable width memory module. The configurable width buffer device includes an interface and a configurable serialization circuit capable of varying a data path width or a number of contacts used at the interface of the configurable width buffer device in accessing the at least one memory device. In an alternate embodiment of the present invention, a multiplexer/demultiplexer circuit is provided. A state storage provides a data width for the configurable width buffer and a SPD provides the configurable width buffer and/or module capabilities to the memory system.
277 Citations
50 Claims
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1. A memory module comprising:
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a connector interface which includes a first contact and a second contact;
a first integrated circuit having memory including a first storage cell and a second storage cell; and
a buffer device coupled to the first integrated circuit and the connector interface, wherein the buffer device is operable in a first mode and a second mode, wherein;
during the first mode of operation, the first storage cell and the second storage cell are accessible from the first contact; and
during the second mode of operation, the first storage cell is accessible from the first contact and the second storage cell is accessible from the second contact. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19)
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20. A memory module comprising:
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a connector interface which includes a first contact and a second contact;
a first integrated circuit having memory including a first storage cell;
a second integrated circuit having memory including a second storage cell; and
a buffer device coupled to the first integrated circuit, the second integrated circuit and the connector interface, wherein the buffer device is operable in a first mode and a second mode, wherein;
during the first mode of operation, the first storage cell and the second storage cell are accessible from the first contact; and
during a second mode of operation, the first storage cell is accessible from the first contact and the second storage cell is accessible from the second contact. - View Dependent Claims (21, 22, 23, 24, 25, 26, 27, 28)
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29. A memory module comprising:
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at least one integrated circuit having memory disposed on the module; and
a buffer device including;
a memory interface to communicate with the at least one integrated circuit memory device; and
a controller interface to communicate with a controller device, wherein the controller interface includes a configurable number of interface circuits to configure how many parallel signaling paths the controller device uses to access the at least one integrated circuit via the buffer device. - View Dependent Claims (30, 31, 32, 33, 34)
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35. An integrated circuit buffer device comprising:
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an interface port to communicate with at least one integrated circuit having memory, wherein the interface port includes a first transceiver circuit and a second transceiver circuit;
a configurable port interface to communicate with a controller device, wherein the configurable port interface includes a third transceiver circuit and a fourth transceiver circuit, wherein;
in a first configuration, the first transceiver circuit and the second transceiver circuit are coupled to the third transceiver circuit; and
in a second configuration, the first transceiver circuit is coupled to the third transceiver circuit and the second transceiver circuit is coupled to the fourth transceiver circuit. - View Dependent Claims (36, 37, 38, 39, 40)
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41. A buffer device comprising:
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a first interface to communicate with at least one integrated circuit having memory; and
a second interface, coupled to the first interface, to communicate with a controller device, wherein the second interface includes a configurable number of interface circuits to configure how many parallel signaling paths are used to access the at least one integrated circuit via the buffer device. - View Dependent Claims (42, 43, 44, 45, 46, 47, 48)
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49. A buffer device comprising:
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memory interface means for communicating with at least one integrated circuit having memory; and
controller interface means for configuring how many parallel signaling paths a controller device uses to access the at least one integrated circuit memory via the buffer device. - View Dependent Claims (50)
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Specification