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Method of timing calibration using slower data rate pattern

  • US 20040187046A1
  • Filed: 01/30/2004
  • Published: 09/23/2004
  • Est. Priority Date: 11/09/2000
  • Status: Active Grant
First Claim
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1. A method of calibrating a digital circuit, comprising:

  • receiving a calibration bit pattern at a first logic device;

    storing said received calibration bit pattern at said first logic device;

    using said stored first calibration pattern during subsequent calibration operations to adjust a relative timing of clock and data signals on at least one data path of said first logic device to produce a reliable detection of said calibration bit pattern.

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