Method of timing calibration using slower data rate pattern
First Claim
1. A method of calibrating a digital circuit, comprising:
- receiving a calibration bit pattern at a first logic device;
storing said received calibration bit pattern at said first logic device;
using said stored first calibration pattern during subsequent calibration operations to adjust a relative timing of clock and data signals on at least one data path of said first logic device to produce a reliable detection of said calibration bit pattern.
1 Assignment
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Accused Products
Abstract
An improved technique and associated apparatus for timing calibration of a logic device is provided. A calibration test pattern is transferred to a logic device first at a data rate slower than normal operating speed to ensure correct capture of the pattern at the device to be calibrated. Once the pattern is correctly captured and stored, the test pattern is transmitted to the logic device at the normal operating data rate to perform timing calibration. The improved technique and apparatus permits the use of any pattern of bits as a calibration test pattern, programmable by the user or using easily-interchangeable hardware.
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Citations
186 Claims
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1. A method of calibrating a digital circuit, comprising:
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receiving a calibration bit pattern at a first logic device;
storing said received calibration bit pattern at said first logic device;
using said stored first calibration pattern during subsequent calibration operations to adjust a relative timing of clock and data signals on at least one data path of said first logic device to produce a reliable detection of said calibration bit pattern. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27)
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28. A method of calibrating a digital circuit, comprising:
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providing a first calibration bit pattern at a location external to a first logic device;
transmitting said first calibration pattern to said first logic device;
storing said transmitted first calibration pattern at said first logic device;
producing a first calibration signal by repeating said first calibration pattern;
applying said repeating first calibration signal to at least one data path of said first logic device; and
using said stored first calibration pattern, said applied first calibration signal and a clock signal at said first logic device to adjust a relative timing of clock and data signals on at least one data path of said first logic device to produce a reliable detection of said calibration bit pattern on said at least one data path. - View Dependent Claims (29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58)
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59. A method of calibrating a digital circuit, comprising:
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providing a first calibration bit pattern to a first logic device;
transmitting said first calibration pattern from said first logic device to a second logic device;
storing said transmitted first calibration pattern at said second logic device;
producing a first calibration signal by repeating said first calibration pattern at said second logic device;
applying said repeating first calibration signal to at least one data path of said first logic device; and
using said provided first calibration pattern, said applied first calibration signal and a clock signal at said first logic device to adjust a relative timing of clock and data signals on at least one data path of said first logic device to produce a reliable detection of said calibration bit pattern on said at least one data path. - View Dependent Claims (60, 61, 62, 63, 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, 80, 81, 82, 83, 84, 85, 86, 87, 88, 89, 90, 91, 92, 93, 94, 95, 96, 97, 98, 99, 100, 101, 102, 103, 104)
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105. A digital circuit for calibrating an incoming signal path of a logic device, comprising:
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an incoming pattern signal path;
a pattern storage device;
at least one incoming data signal path;
at least one variable delay circuit, respectively provided in said incoming data signal path or a clock signal path;
a control logic circuit connected to receive a calibration pattern signal including a calibration bit pattern on said incoming pattern signal path and store said calibration bit pattern in said pattern storage device, said control logic circuit subsequently using said stored calibration bit pattern and a clock signal during calibration operations to adjust said variable delay circuit to a delay value which produces a reliable detection of said stored calibration bit pattern within a calibration data signal received on said at least one incoming data signal path. - View Dependent Claims (106, 107, 108, 109, 110, 111, 112, 113, 114, 115, 116, 117, 118, 119, 120, 121)
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122. A logic device, comprising:
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an incoming pattern signal path;
a pattern storage device;
at least one incoming data signal path;
at least one variable delay circuit, respectively provided in said incoming data signal path or a clock signal path;
a control logic circuit connected to receive a calibration pattern signal including a calibration bit pattern on said incoming pattern signal path and store said calibration bit pattern in said pattern storage device, said control logic circuit subsequently using said stored calibration bit pattern and a clock signal during calibration operations to adjust said variable delay circuit to a delay value which produces a reliable detection of said stored calibration bit pattern within a calibration data signal received on said incoming data signal path. - View Dependent Claims (123, 124, 125, 126, 127, 128, 129, 130, 131, 132, 133, 134, 135, 136, 137, 138)
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139. A digital logic system, comprising:
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a first logic device;
a second logic device connected to said first logic device; and
a calibration circuit on at least one of said first and second logic devices, said calibration circuit comprising;
an incoming pattern signal path;
a pattern storage device;
at least one incoming data signal path;
at least one variable delay circuit, respectively provided in said incoming data signal path or a clock signal path;
a control logic circuit connected to receive a calibration pattern signal including a calibration bit pattern on said incoming pattern signal path and store said calibration bit pattern in said pattern storage device, said control logic circuit subsequently using said stored calibration bit pattern and a clock signal during calibration operations to adjust said variable delay circuit to a delay value which produces a reliable detection of said stored calibration bit pattern within a calibration data signal received on said at least one incoming data signal path. - View Dependent Claims (140, 141, 142, 143, 144, 145, 146, 147, 148, 149, 150, 151, 152, 153, 154, 155, 156, 157, 158, 159, 160, 161, 162, 163, 164, 165, 166, 167, 168, 169)
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170. A processor system, comprising:
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a processor; and
an integrated memory circuit connected to said processor, at least one of said integrated memory circuit and processor including at least one calibration circuit comprising;
a incoming pattern signal path;
a pattern storage device;
at least one incoming data signal path;
at least one variable delay circuit, respectively provided in said incoming data signal path or a clock signal path;
a control logic circuit connected to receive a calibration pattern on said incoming pattern signal path and store said calibration pattern in said pattern storage device, said control logic circuit subsequently using said stored calibration pattern and a clock signal during calibration operations to adjust said variable delay circuit to a delay value which produces a reliable detection of said calibration pattern within a calibration signal received on said at least one incoming data signal path. - View Dependent Claims (171, 172, 173, 174, 175, 176, 177, 178, 179, 180, 181, 182, 183, 184, 185, 186)
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Specification