Non-stalling circular counterflow pipeline processor with reorder buffer
First Claim
1. In a computer system having a plurality of threads, including a first and second thread, a method of executing more than one thread at a time, the method comprising:
- providing a first and a second reorder buffer;
reading first instructions and first operands associated with the first thread from the first reorder buffer;
executing one of the first instructions and storing a result in the first reorder buffer, wherein storing the result includes marking the result with a tag associating the result with the first thread;
reading second instructions and second operands associated with the second thread from the second reorder buffer; and
executing one of the second instructions and storing a result in the second reorder buffer, wherein storing the result includes marking the result with a tag associating the result with the second thread.
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Abstract
A system and method of executing instructions within a counterflow pipeline processor. The counterflow pipeline processor includes an instruction pipeline, a data pipeline, a reorder buffer and a plurality of execution units. An instruction and one or more operands issue into the instruction pipeline and a determination is made at one of the execution units whether the instruction is ready for execution. If so, the operands are loaded into the execution unit and the instruction executes. The execution unit is monitored for a result and, when the result arrives, it is stored into the result pipeline. If the instruction reaches the end of the pipeline without executing it wraps around and is sent down the instruction pipeline again.
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Citations
20 Claims
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1. In a computer system having a plurality of threads, including a first and second thread, a method of executing more than one thread at a time, the method comprising:
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providing a first and a second reorder buffer;
reading first instructions and first operands associated with the first thread from the first reorder buffer;
executing one of the first instructions and storing a result in the first reorder buffer, wherein storing the result includes marking the result with a tag associating the result with the first thread;
reading second instructions and second operands associated with the second thread from the second reorder buffer; and
executing one of the second instructions and storing a result in the second reorder buffer, wherein storing the result includes marking the result with a tag associating the result with the second thread. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12)
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13. A processor comprising:
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an instruction pipeline; and
a results pipeline, wherein the instruction pipeline and the results pipeline are counter rotating queues;
a first execution unit in communication with the results and instruction pipelines;
a plurality of threads including a first and second thread;
a first and a second reorder buffer, the first reorder buffer associated with the first thread and the second reorder buffer associated with the second thread; and
a first instruction fetch/decode unit. - View Dependent Claims (14, 15, 16, 17, 18, 19, 20)
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Specification