Semiconductor device and a method of manufacturing the same

• US 20040188707A1
• Filed: 03/26/2004
• Published: 09/30/2004
• Est. Priority Date: 03/26/2003
• Status: Active Grant

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: Renesas Technology Corporation (Renesas Electronics Corporation)
• Inventors: Inagawa, Hiroshi, Kurokawa, Atsushi, Imamura, Yoshinori, Kitahara, Toshiaki
• Granted Patent: US 7,029,938 B2
• Time in Patent Office: Days
• US Class Current: 257/192
• CPC Class Codes: H01L 29/0657 characterised by the shape of the body
• CPC Class Codes: H01L 29/41708 Emitter or collector electrodes for bipolar transistors
• CPC Class Codes: H01L 29/42304 Base electrodes for bipolar transistors
• CPC Class Codes: H01L 29/66318 Heterojunction transistors
• CPC Class Codes: H01L 29/7371 Vertical transistors

Abstract

Provided is a technique of improving the properties of a bipolar transistor. Described specifically, upon formation of a collector electrode around a base mesa by the lift-off method, a resist film is formed over connection portions between the outer periphery of a region OA1 and a region in which the base mesa 4a is formed, followed by successive formation of gold germanium (AuGe), nickel (Ni) and Au in the order of mention over the entire surface of a substrate so that the stacked film of them will not become an isolated pattern. As a result, the stacked film over the base mesa 4a is connected to a stacked film at the outer periphery of the region OA1, facilitating peeling of the stacked film over the base mesa 4a. In addition, generation of side etching upon formation of a via hole extending from the back side of the substrate to a backside via electrode is reduced by forming the backside via electrode using a material such as WSi which hardly reacts with an n type GaAs layer or n type InGaAs layer.

Claims

1. A method of manufacturing a semiconductor device, comprising a step of:

(a) forming a pattern in a second region encompassing therewith a first region over a semiconductor substrate,

the step (a) including steps of;

(b) forming a first film over the first region, a third region encompassing therewith the second region, and first and second connection portions connecting the first region and the third region;

(c) after the step (b), forming a second film over the semiconductor substrate; and

(d) after the step (c), removing the first film to remove the second film over the first region, the third region and the first and second connection portions, and thereby forming two patterns comprised of the second film over the second region.

2. A method of manufacturing a semiconductor device according to claim 1, wherein the first film is a photoresist film and the second film is a conductive film.

3. A method of manufacturing a semiconductor device according to claim 1,

wherein the first region and the third region are connected in a first direction via the first and second connection portions, and

wherein the width of each of the first and second connection portions in a second direction vertical to the first direction is smaller than the width of the first region in the second direction.

4. A method of manufacturing a semiconductor device according to claim 1, further comprising a step of:

(e) forming another conductive film for electrically connecting the two patterns after the step (d), wherein the second film is a conductive film.

5. A method of manufacturing a semiconductor device according to claim 1, wherein the semiconductor substrate or a film just below the two patterns is comprised of a compound semiconductor.

6. A method of manufacturing a semiconductor device according to claim 5, wherein the semiconductor substrate or the film just below the two patterns is comprised of gallium arsenide (GaAs) or indium phosphide (InP).

7. A method of manufacturing a semiconductor device according to claim 6, wherein the second film is a film having gold (Au) as a main component.

8. A method of manufacturing a semiconductor device according to claim 1,

wherein the semiconductor device includes a bipolar transistor having a collector layer formed in the first region and the second region, a base layer formed over the first region of the collector layer, and an emitter layer formed over the base layer, and

wherein the two patterns are collector electrodes formed over the second region of the collector layer.

9. A method of manufacturing a semiconductor device according to claim 1, wherein the first region has a substantially circular shape or a circular shape with a portion cut out thereof.

10. A method of manufacturing a semiconductor device according to claim 1, wherein the first and second connection portions are arranged substantially symmetrical relative to the first region.

11-18. -18. (Cancelled)

19. A method of manufacturing a semiconductor device comprising steps of:

(a) preparing a substrate having a first main surface and a second main surface opposite thereto;

(b) forming a compound semiconductor layer over the first main surface;

(c) forming, over the compound semiconductor layer, a first conductive film comprised of a refractory metal, or a nitride or silicide thereof;

(d) forming an opening portion extending from the second main surface and reaching the first conductive film; and

(e) forming a second conductive film over the second main surface and in the opening portion.

20. A method of manufacturing a semiconductor device according to claim 19, wherein the step (d) comprises wet processing.

21. A method of manufacturing a semiconductor device according to claim 19, wherein the first conductive film is comprised of tungsten silicide (WSi), titanium tungsten (TiW) or titanium (Ti).

22. A method of manufacturing a semiconductor device according to claim 19, wherein the compound semiconductor layer contains gallium arsenide (GaAs) or indium phosphide (InP).

23. A method of manufacturing a semiconductor device according to claim 19, further comprising the steps of:

(f1) forming, over the first main surface, a first semiconductor region having a first conductivity type;

(f2) forming a second semiconductor region having a second conductivity type, which is a conductivity type opposite to the first conductivity type, over the first semiconductor region;

(f3) forming a third semiconductor region having the first conductivity type over the second semiconductor region; and

(f4) forming first to third electrodes electrically connected to the first to third semiconductor regions, respectively,

(g) wherein the third electrode and the first conductive film are formed in the same step.