Three-dimensional memory device incorporating segmented bit line memory array

• US 20040188714A1
• Filed: 03/31/2003
• Published: 09/30/2004
• Est. Priority Date: 03/31/2003
• Status: Active Grant

• Current Assignee: Woden Technologies Inc. (Wi-LAN Inc.)
• Original Assignee: SanDisk 3D LLC (Western Digital Corporation)
• Inventors: Scheuerlein, Roy E., Fasoli, Luca, Ilkbahar, Alper
• Granted Patent: US 7,233,024 B2
• Time in Patent Office: Days
• US Class Current: 257/200
• CPC Class Codes: G11C 16/0416 comprising cells containing a single floating gate transistor and no select transistor, e.g. UV EPROM
• CPC Class Codes: G11C 16/0466 comprising cells with charge storage in an insulating layer, e.g. metal-nitride-oxide-silicon [MNOS], silicon-oxide-nitride-oxide-silicon [SONOS] G11C16/0483, G11C16/0491 take precedence
• CPC Class Codes: G11C 17/12 using field-effect devices
• CPC Class Codes: G11C 17/18 Auxiliary circuits, e.g. for writing into memory
• CPC Class Codes: G11C 2213/71 Three dimensional array
• CPC Class Codes: G11C 2213/77 Array wherein the memory element being directly connected to the bit lines and word lines without any access device being used
• CPC Class Codes: G11C 7/18 Bit line organisation; Bit line lay-out
• CPC Class Codes: Y10S 257/91 Diode arrays, e.g. diode read-only memory array

Abstract

A three-dimensional (3D) high density memory array includes multiple layers of segmented bit lines (i.e., sense lines) with segment switch devices within the memory array that connect the segments to global bit lines. The segment switch devices reside on one or more layers of the integrated circuit, preferably residing on each bit line layer. The global bit lines reside preferably on one layer below the memory array, but may reside on more than one layer. The bit line segments preferably share vertical connections to an associated global bit line. In certain EEPROM embodiments, the array includes multiple layers of segmented bit lines with segment connection switches on multiple layers and shared vertical connections to a global bit line layer. Such memory arrays may be realized with much less write-disturb effects for half selected memory cells, and may be realized with a much smaller block of cells to be erased.

Claims

1. An integrated circuit comprising:

a three-dimensional memory array having a respective plurality of segmented array lines of a first type on each of at least one layer of the memory array;

a plurality of global array lines on at least one layer of the memory array; and

a respective plurality of segment switch devices on each of at least one memory plane of the memory array, each for coupling one or more segmented array lines of the first type to an associated global array line.

2. The integrated circuit of claim 1 further comprising a plurality of shared vertical connections in the memory array, each providing a connection path for at least two segmented array lines of the first type, to an associated global array line.

3. The integrated circuit of claim 1 further comprising a plurality of shared vertical connections in the memory array, each providing a connection path for at least one segmented array line of the first type on each of at least two layers, to an associated global array line.

4. The integrated circuit of claim 1 wherein the global array lines run generally parallel to the segmented array lines of the first type.

5. The integrated circuit of claim 1 further comprising:

a respective segment switch device for coupling each segmented array line of the first type to its associated global array line.

6. The integrated circuit of claim 1 wherein the respective plurality of segmented array lines of the first type on at least two memory array layers are different in number.

7. The integrated circuit of claim 1 wherein a respective plurality of segment switch devices on at least two memory planes are different in number.

8. The integrated circuit of claim 1 wherein the plurality of segmented array lines of the first type on at least one memory array layer is different in number than the plurality of segment switch devices on at least one layer of the memory array.

9. The integrated circuit of claim 1 comprising passive element memory cells.

10. The integrated circuit of claim 9 comprising anti-fuse memory cells.

11. The integrated circuit of claim 1 comprising EEPROM memory cells.

12. The integrated circuit of claim 1 comprising more than one type of memory cells within the three-dimensional memory array.

13. The integrated circuit of claim 1 comprising memory cells having a switch device.

14. The integrated circuit of claim 13 comprising memory cell switch devices having a permanently modifiable threshold voltage.

15. The integrated circuit of claim 13 comprising memory cell switch devices which include a charge storage dielectric.

16. The integrated circuit of claim 15 comprising SONOS memory cell switch devices.

17. The integrated circuit of claim 13 comprising memory cells including a capacitor to store memory state.

18. The integrated circuit of claim 13 comprising memory cells including a ferro-electric material.

19. The integrated circuit of claim 13 comprising segment switch devices which are substantially identical in structure to the memory cell switch devices.

20. The integrated circuit of claim 13 comprising segment switch devices which are substantially different in structure than the memory cell switch devices.

21. The integrated circuit of claim 1 further comprising:

a respective plurality of bias segment lines on each of at least one memory array layer, each associated with at least one segmented array line of the first type on the same memory array layer.

22. The integrated circuit of claim 1 wherein at least one array line layer is shared by two vertically adjacent array line layers.

23. An integrated circuit comprising:

a three-dimensional memory array having a respective plurality of word lines on each of at least one layer of the memory array, having a respective plurality of bit line segments on each of at least one layer of the memory array, defining a memory layer for each vertically adjacent word line layer and segmented bit line layer, each memory layer comprising a plurality of memory segments;

a respective plurality of global bit lines on each of at least a first global bit line layer;

Wherein each memory segment comprises a segment switch device for coupling the bit line segment to an associated global bit line.

24. The integrated circuit of claim 23 further comprising a plurality of shared vertical connections in the memory array, each providing a connection path for at least two bit line segments to an associated global bit line.

25. The integrated circuit of claim 23 further comprising a plurality of shared vertical connections in the memory array, each providing a connection path for at least one bit line segment on each of at least two layers to an associated global bit line.

26. The integrated circuit of claim 23 comprising EEPROM memory cells.

27. The integrated circuit of claim 23 wherein the global bit lines run generally parallel to the bit line segments.

28. The integrated circuit of claim 27 comprising global bit lines having a resistance per unit length which is a least a factor of 5 lower than that of a bit line segment.

29. The integrated circuit of claim 27 comprising global bit lines having a capacitance per unit length which is a least a factor of 5 lower than that of a bit line segment.

30. The integrated circuit of claim 23 comprising more than one type of memory cells within the three-dimensional memory array.

31. The integrated circuit of claim 23 comprising memory cells having a switch device.

32. The integrated circuit of claim 31 comprising memory cell switch devices having a permanently modifiable threshold voltage.

33. The integrated circuit of claim 31 comprising memory cell switch devices which include a charge storage dielectric.

34. The integrated circuit of claim 33 comprising SONOS memory cell switch devices.

35. The integrated circuit of claim 31 comprising memory cells including a capacitor to store memory state.

36. The integrated circuit of claim 31 comprising memory cells including a ferro-electric material.

37. The integrated circuit of claim 31 comprising segment switch devices which are substantially identical in structure to the memory cell switch devices.

38. The integrated circuit of claim 31 comprising segment switch devices which are substantially different in structure than the memory cell switch devices.

39. The integrated circuit of claim 38 comprising SONOS memory cell devices.

40. The integrated circuit of claim 39 comprising segment switch devices which contain no nitride but are otherwise substantially identical to the memory cell switch devices.

41. The integrated circuit of claim 23 comprising passive element memory cells.

42. The integrated circuit of claim 41 comprising anti-fuse memory cells.

43. The integrated circuit of claim 23 further comprising:

a respective plurality of global bias lines on at least a first global bias line layer;

wherein each memory segment comprises a respective bias line segment and a respective bias switch device for coupling the respective bias line segment to an associated global bias line.

44. The integrated circuit of claim 23 wherein respective pairs of adjacent memory segments are associated with a single respective bit line segment disposed therebetween, having a respective segment switch device for coupling the respective bit line segment to an associated global bit line.

45. The integrated circuit of claim 44 further comprising:

a respective plurality of global bias lines on at least a first global bias line layer; and

wherein respective pairs of adjacent memory segments are associated with a respective bias line segment therebetween, having a respective bias switch device for coupling the respective bias line segment to an associated global bias line.

46. The integrated circuit of claim 45 wherein:

wherein adjacent memory segments associated with the same bit line segment are associated with different global bias lines.

47. The integrated circuit of claim 23 wherein:

the array comprises a plurality of sub-arrays; and

further comprising global bit line circuits each shared by a respective pair of adjacent sub-arrays, but disposed substantially beneath only one of the pair of adjacent sub-arrays.

48. An integrated circuit comprising:

a three-dimensional memory array having a respective plurality of word lines on each of at least one layer of the memory array, having a respective plurality of bit line segments on each of at least two layers of the memory array, defining a memory layer for each vertically adjacent word line layer and segmented bit line layer; and

a respective plurality of global bit lines on each of at least a first global bit line layer;

a respective plurality of memory segments on each of said memory layers, each memory segment comprising

a respective plurality of memory cells coupled to a respective bit line segment; and

a respective segment switch device for coupling the respective bit line segment to an associated global bit line by way of a vertical connection which is shared by at least one memory segment on each of at least two memory layers.

49. The integrated circuit of claim 48 wherein at least two bit line segments on a given layer having word lines in common share a vertical connection to an associated global bit line.

50. The integrated circuit of claim 49 wherein each of the at least two bit line segments on a given layer having word lines in common that share a vertical connection to an associated global bit line, have a different segment control signal for its respective segment switch device.

51. The integrated circuit of claim 50 comprising memory cells including a charge storage dielectric.

52. The integrated circuit of claim 50 comprising memory cells including a capacitor for storing memory state.

53. The integrated circuit of claim 50 comprising memory cells including a ferro-electric material.

54. The integrated circuit of claim 48 wherein at least two bit line segments on a given layer that do not have word lines in common, each share a vertical connection to an associated global bit line.

55. The integrated circuit of claim 54 comprising passive element memory cells.

56. The integrated circuit of claim 54 comprising memory cells including a switch device.

57. The integrated circuit of claim 54 wherein at least two bit line segments on a given layer having a first plurality of word lines in common share a vertical connection to an associated global bit line with at least two other bit line segments on the given layer having a second plurality of word lines in common.

58. The integrated circuit of claim 48 wherein the bit line segments on a given layer are interleaved such that at least two bit line segments sharing word lines in common are coupled at opposite ends thereof to an associated global bit line.

59. The integrated circuit of claim 58 wherein a pair of interleaved bit line segments on the given layer are coupled at opposite ends thereof to a single global bit line.

60. The integrated circuit of claim 59 comprising passive element memory cells.

61. The integrated circuit of claim 48 comprising a single global bit line layer disposed below the memory layers.

62. The integrated circuit of claim 48 comprising a first global bit line layer and a second global bit line layer.

63. The integrated circuit of claim 62 wherein:

the first global bit line layer is disposed below the memory layers; and

the second global bit line layer is disposed above the memory layers.

64. The integrated circuit of claim 62 wherein half of the bit line segments on a given layer are associated with the first global bit line layer, and the other half associated with the second global bit line layer.

65. The integrated circuit of claim 62 wherein:

bit line segments on a given layer are associated with either the first global bit line layer or the second global bit line layer; and

bit line segments on each of a first set of memory layers are associated with the first global bit line layer, and bit line segments on each of a second set of memory layers are associated with the second global bit line layer.

66. The integrated circuit of claim 62 wherein at least one word line layer is shared by two bit line layers, one such bit line layer associated with the first global bit line layer, and the other such bit line layer associated with the second global bit line layer.

67. The integrated circuit of claim 48 wherein at least one word line or bit line layer is shared by two vertically adjacent memory layers.

68. The integrated circuit of claim 67 wherein at least one word line layer is shared by two bit line layers, both such bit line layers associated with a single global bit line layer.

69. The integrated circuit of claim 48 comprising memory segments including a respective bias line segment coupled to an associated global bias line.

70. The integrated circuit of claim 69 comprising memory cells including a capacitor for storing memory state.

71. The integrated circuit of claim 48 further comprising:

a respective plurality of global bias lines on at least a first global bias line layer;

wherein each memory segment further comprises a respective bias line segment and a respective bias switch device for coupling the respective bias line segment to an associated global bias line.

72. The integrated circuit of claim 71 comprising memory cells including a ferro-electric material.

73. The integrated circuit of claim 71 wherein the global bias lines run parallel to the word lines.

74. The integrated circuit of claim 71 wherein at least two memory segments on a given layer having word lines in common share a vertical connection to an associated global bias line.

75. The integrated circuit of claim 74 wherein each of the at least two memory segments on a given layer having word lines in common that share a vertical connection to an associated global bias line, have a different bias segment control signal for its respective bias switch device.

76. The integrated circuit of claim 75 comprising SONOS memory cells.

77. The integrated circuit of claim 75 comprising memory cells having a ferro-electric material.

78. The integrated circuit of claim 75 comprising memory cells having a switch device with a permanently modifiable threshold voltage.

79. The integrated circuit of claim 74 wherein each of the at least two memory segments on a given layer having word lines in common that share a vertical connection to an associated global bias line, have a respective bias switch device controlled by the same bias segment control signal.

80. The integrated circuit of claim 71 wherein at least two memory segments on a given layer that do not have word lines in common, each share a vertical connection to an associated global bias line.

81. The integrated circuit of claim 80 wherein at least two memory segments on a given layer having a first plurality of word lines in common share a vertical connection to an associated global bias line with at least two other memory segments on the given layer having a second plurality of word lines in common.

82. The integrated circuit of claim 71 wherein the bit line segments on a given layer are interleaved such that at least two bit line segments sharing word lines in common are coupled at opposite ends thereof to an associated global bit line.

83. The integrated circuit of claim 71 wherein:

the bias line segments on a given layer are associated with either a first global bias line layer or a second global bias line layer; and

the bias line segments on each of a first set of memory layers are associated with the first global bias line layer, and the bias line segments on each of a second set of memory layers are associated with the second global bias line layer.

84. The integrated circuit of claim 83 wherein:

at least one word line layer is shared by two bit line layers; and

the bias line segments on half of the memory layers are associated with the first global bias line layer, and the bias line segments on the other half are associated with the second global bias line layer.

85. A computer readable medium encoding an integrated circuit, said encoded integrated circuit comprising:

a three-dimensional memory array having a respective plurality of segmented array lines of a first type on each of at least one layer of the memory array;

a plurality of global array lines on at least one layer of the memory array; and

a respective plurality of segment switch devices on each of at least one memory plane of the memory array, each for coupling one or more segmented array lines of the first type to an associated global array line.

86. The computer readable medium of claim 85 wherein the encoded integrated circuit further comprises a plurality of shared vertical connections in the memory array, each providing a connection path for at least two segmented array lines of the first type, to an associated global array line.

87. The computer readable medium of claim 85 wherein the encoded integrated circuit further comprises a plurality of shared vertical connections in the memory array, each providing a connection path for at least one segmented array line of the first type on each of at least two layers, to an associated global array line.

88. The computer readable medium of claim 85 wherein the encoded integrated circuit further comprises a respective segment switch device for coupling each segmented array line of the first type to its associated global array line.

89. The computer readable medium of claim 85 wherein the encoded integrated circuit further comprises passive element memory cells.

90. The computer readable medium of claim 89 wherein the encoded integrated circuit further comprises anti-fuse memory cells.

91. The computer readable medium of claim 85 wherein the encoded integrated circuit further comprises EEPROM memory cells.

92. The computer readable medium of claim 85 wherein the encoded integrated circuit comprises more than one type of memory cells within the three-dimensional memory array.

93. The computer readable medium of claim 85 wherein the encoded integrated circuit further comprises memory cells having a switch device.

94. The computer readable medium of claim 93 wherein the encoded integrated circuit further comprises memory cell switch devices having a permanently modifiable threshold voltage.

95. The computer readable medium of claim 93 wherein the encoded integrated circuit comprises memory cell switch devices which include a charge storage dielectric.

96. The computer readable medium of claim 95 wherein the encoded integrated circuit comprises SONOS memory cell switch devices.

97. The computer readable medium of claim 93 wherein the encoded integrated circuit comprises segment switch devices which are substantially identical in structure to the memory cell switch devices.

98. The computer readable medium of claim 93 wherein the encoded integrated circuit comprises segment switch devices which are substantially different in structure than the memory cell switch devices.

99. The computer readable medium of claim 85 wherein the encoded integrated circuit further comprises a respective plurality of bias segment lines on each of at least one memory array layer, each associated with at least one segmented array line of the first type on the same memory array layer.

100. The computer readable medium of claim 85 wherein the encoded integrated circuit comprises at least one array line layer which is shared by two vertically adjacent array line layers.