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Whole chip ESD protection

  • US 20040188764A1
  • Filed: 04/08/2004
  • Published: 09/30/2004
  • Est. Priority Date: 07/25/2002
  • Status: Active Grant
First Claim
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1. A whole chip electrostatic discharge, ECD, first embodiment circuit comprising:

  • a PN diode whose p-side connects to the input/output, I/O pad to be protected and whose N-side is connected to Vcc supply voltage, a PMOS FET plus NMOS FET 2-device input stage connected between Vcc and Vss, a resistor plus NMOS FET first mid stage connected between Vcc and Vss (ground), a resistor to ground second mid-stage, and a PMOS FET plus NMOS FET output stage connected between Vcc and Vss (ground) whose input connects from the mid stages and whose output drives an unused I/O pad.

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