Semiconductor device

• US 20040188857A1
• Filed: 03/26/2004
• Published: 09/30/2004
• Est. Priority Date: 03/27/2003
• Status: Active Grant

• Current Assignee: Socionext Inc.
• Original Assignee: Matsushita Electric Industrial Company Limited (Panasonic Holdings Corporation)
• Inventors: Nakayama, Tomoyuki, Ohnishi, Manabu, Nagai, Noriyuki, Takemura, Koji, Doi, Atsushi, Huh, Hoyeun
• Granted Patent: US 7,030,503 B2
• Time in Patent Office: Days
• US Class Current: 257/778
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/05552 in top view
• CPC Class Codes: H01L 2224/05555 being circular or elliptic
• CPC Class Codes: H01L 2224/06153 with a staggered arrangement, e.g. depopulated array
• CPC Class Codes: H01L 23/3114 the device being a chip scale package, e.g. CSP
• CPC Class Codes: H01L 23/50 for integrated circuit devices, e.g. power bus, number of leadsH01L23/482 - H01L23/498 take precedence
• CPC Class Codes: H01L 24/06 of a plurality of bonding areas
• CPC Class Codes: H01L 2924/00012 Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/01004 Beryllium [Be]
• CPC Class Codes: H01L 2924/01005 Boron [B]
• CPC Class Codes: H01L 2924/01006 Carbon [C]
• CPC Class Codes: H01L 2924/01033 Arsenic [As]
• CPC Class Codes: H01L 2924/01076 Osmium [Os]
• CPC Class Codes: H01L 2924/01079 Gold [Au]
• CPC Class Codes: H01L 2924/01082 Lead [Pb]
• CPC Class Codes: H01L 2924/14 Integrated circuits
• CPC Class Codes: H01L 2924/3011 Impedance

Abstract

Input/output cells are formed so as to be peripherally arranged adjacent to a corner cell on a surface of a semiconductor chip, and electrode pads are formed on the respective input/output cells. The electrode pads are configured in a zigzag pad arrangement so as to form inner and outer pad arrays. However, of the electrode pads forming the inner pad array, those electrode pads in predetermined areas adjacent to the two sides of the corner cell are not disposed, such that an interconnect pattern of a carrier which is bump-bonded to the semiconductor chip and vias are prevented from becoming complex.

Claims

1. A semiconductor device formed by flip-chip bonding a semiconductor chip to a carrier used for external connection with the semiconductor chip, wherein:

the semiconductor chip includes;

a plurality of input/output cells including circuit elements formed so as to be peripherally arranged on a surface of the semiconductor chip, and

a plurality of electrode pads formed on associated ones of the input/output cells;

the electrode pads are configured in a zigzag pad arrangement so as to form inner and outer pad arrays; and

a predetermined area near a corner on the semiconductor chip surface is designated as a pad-disposition restriction area, within which disposing and usage of one or ones of the electrode pads that are bump-bonded to an interconnect pattern formed on a surface of the carrier are restricted.

2. The device of claim 1, wherein each of the electrode pads has a tenon-like conformation in plan view, and includes a narrow, probing portion for testing or analyzing, and a wide, bonding portion which is bump-bonded to the interconnect pattern on the carrier surface.

3. The device of claim 1, wherein the extent of the pad-disposition restriction area is determined in accordance with design rules for the carrier.

4. The device of claim 1, wherein in the pad-disposition restriction area, part of the inner pad array is not formed.

5. The device of claim 4, wherein in the pad-disposition restriction area, a pitch for the outer pad array is reduced in accordance with minimum separation rules regarding disposition of the input/output cells.

6. The device of claim 1, wherein in the pad-disposition restriction area, neither the inner pad array nor the outer pad array is formed.

7. The device of claim 6, wherein in the pad-disposition restriction area, instead of some of the input/output cells which correspond to the inner and outer pad arrays, other types of function cells are disposed.

8. The device of claim 1, wherein in the pad-disposition restriction area, the inner pad array includes probing-specific pads for testing or analyzing, and is not bump-bonded to the interconnect pattern on the carrier surface.

9. The device of claim 1, wherein in the pad-disposition restriction area, only one or ones of the electrode pads of the inner pad array are individually bump-bonded to the interconnect pattern on the carrier surface.

10. The device of claim 1, wherein in the pad-disposition restriction area, the inner pad array is individually bump-bonded to the interconnect pattern on the carrier surface, and at least two of the electrode pads are short-circuited to each other inside the carrier.

11. The device of claim 10, wherein the electrode pads that are short-circuited to each other inside the carrier are connected via the carrier to a power supply or to ground.

12. The device of claim 10, wherein of the input/output cells, those corresponding to the electrode pads that are short-circuited to each other inside the carrier function as a single high-drive-current capability cell.

13. The device of claim 10, wherein of the input/output cells, those corresponding to the electrode pads that are short-circuited to each other inside the carrier function as a single low-impedance cell.