Apparatus and method for disturb-free programming of passive element memory cells

• US 20040190359A1
• Filed: 03/31/2003
• Published: 09/30/2004
• Est. Priority Date: 03/31/2003
• Status: Active Grant

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: Matrix Semiconductor, Inc. (Western Digital Corporation)
• Inventors: Scheuerlein, Roy E., Knall, N. Johan
• Granted Patent: US 6,822,903 B2
• Time in Patent Office: Days
• US Class Current: 365/225.7
• CPC Class Codes: B82Y 10/00 Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
• CPC Class Codes: G11C 13/0014 comprising cells based on organic memory material
• CPC Class Codes: G11C 17/16 using electrically-fusible links
• CPC Class Codes: G11C 17/165 Memory cells which are electrically programmed to cause a change in resistance, e.g. to permit multiple resistance steps to be programmed rather than conduct to or from non-conduct change of fuses and antifuses digital stores using resistance random access memory elements G11C13/0002
• CPC Class Codes: G11C 2213/71 Three dimensional array
• CPC Class Codes: G11C 2213/72 Array wherein the access device being a diode

Abstract

In a passive element memory array, such as a rail stack array having a continuous semiconductor region along one or both of the array lines, programming a memory cell may disturb nearby memory cells as result of a leakage path along the array line from the selected cell to the adjacent cell. This effect may be reduced substantially by changing the relative timing of the programming pulses applied to the array lines for the selected memory cell, even if the voltages are unchanged. In an exemplary three-dimensional antifuse memory array, a positive-going programming pulse applied to the anode region of the memory cell preferably is timed to lie within the time that a more lightly-doped cathode region is pulsed low.

Claims

1. A method for programming a memory array having at least one memory plane, said array comprising memory cells coupled between an associated one of a respective plurality of array lines on each of two memory array layers, comprising memory cells having an anode region and a cathode region, one of said cathode or anode regions being configured to inject charge to the other region when forward biased, said method comprising:

driving a first array line associated with the injecting region of a selected memory cell to a selected bias voltage for the first array line; and

driving a second array line associated with the non-injecting region of the selected cell to a selected bias voltage for the second array line;

then

driving the first array line to an unselected bias voltage for the first array line; and

driving the second array line to an unselected bias voltage for the second array line, wherein the first array line voltage transitions at least a first percentage toward its unselected bias voltage before the second array line transitions at most a second percentage toward its unselected bias voltage.

2. The method of claim 1 wherein the memory array comprises a three-dimensional array having at least three array line layers defining at least two memory planes.

3. The method of claim 2 wherein the memory array comprises memory cells whose anode region is alternately an upper region of some memory layers and a lower region of vertically adjacent memory layers.

4. The method of claim 2 wherein the memory array comprises memory cells whose anode region is either an upper region of all memory layers, or a lower region of all memory layers.

5. The method of claim 1 wherein the memory array comprises antifuse memory cells.

6. The method of claim 5 wherein the memory array includes memory cells respectively comprising, at least when programmed, a diode having a first semiconductor region of a first conductivity type coupled to a respective one of a plurality of array lines on a first associated array line layer, and having a second semiconductor region of a second conductivity type coupled to a respective one of a plurality of array lines on a second associated array line layer, said second semiconductor region being more lightly doped than the first semiconductor region, said non-injecting region comprising the second semiconductor region, and said injecting region comprising the first semiconductor region.

7. The method of claim 6 wherein the second semiconductor region comprises a lightly-doped n-type (n−

) semiconductor region.

8. The method of claim 6 wherein the second semiconductor region comprises a lightly-doped p-type (p−

) semiconductor region.

9. The method of claim 6 wherein the second semiconductor region is initially formed as an intrinsic region.

10. The method of claim 1 wherein the memory array comprises fuse memory cells.

11. The method of claim 1 wherein the memory array comprises memory cells including a ferro-electric material.

12. The method of claim 1 wherein the memory array comprises memory cells including an organic layer.

13. The method of claim 1 wherein said non-injecting regions comprise lightly-doped semiconductor regions, and said injecting regions comprise more heavily doped semiconductor regions.

14. The method of claim 1 wherein said non-injecting regions comprise lightly-doped semiconductor regions, and said injecting regions comprise a metal.

15. The method of claim 1 wherein:

the first percentage comprises around 50%; and

the second percentage comprises around 50%.

16. The method of claim 1 wherein:

the first percentage comprises around 90%; and

the second percentage comprises around 10%.

17. The method of claim 1 wherein the second array line voltage transitions at least a third percentage toward its selected bias voltage before the first array line transitions at most a fourth percentage toward its selected bias voltage.

18. The method of claim 17 wherein:

the third percentage comprises around 50%; and

the fourth percentage comprises around 50%.

19. The method of claim 17 wherein:

the third percentage comprises around 90%; and

the fourth percentage comprises around 10%.

20. The method of claim 1 wherein each array line associated with a memory cell non-injecting region comprises a continuous semiconductor layer that forms a portion of the respective non-injecting region of respective memory cells associated therewith.

21. The method of claim 1 wherein each array line associated with a memory cell non-injecting region comprises a continuous semiconductor layer that connects to the respective non-injecting region of respective memory cells associated therewith, wherein the continuous semiconductor layer and the non-injecting regions have a different doping density.

22. The method of claim 20 wherein the array comprises at least one layer of rail-stack array lines.

23. The method of claim 22 wherein the rail-stack array lines include a conductor comprising a metal.

24. A method for programming a memory array of antifuse memory cells coupled between a respective array line on one memory array layer and a respective array line on another memory array layer, said memory cells comprising two opposite conductivity type semiconductor regions, one being more lightly-doped than the other, said method comprising:

pulsing for a first time period a first selected array line coupled to the more heavily-doped region of a selected memory cell from an unselected bias voltage to a selected bias voltage; and

pulsing for a second time period a second selected array line coupled to the more lightly-doped region of the selected memory cell from an unselected bias voltage to a selected bias voltage;

wherein the first and second array line pulses are arranged so that the selected memory cell, once programmed, is reversed biased whenever the second selected array line is biased at an intermediate voltage closer to its unselected bias voltage than its selected bias voltage.

25. The method of claim 24 wherein the first and second array line pulses are arranged so that the selected memory cell, once programmed, is reversed biased whenever the second selected array line is biased at an intermediate voltage more than 10% toward its unselected bias voltage relative to its selected bias voltage.

26. The method of claim 24 wherein the memory array comprises a three-dimensional array having at least three array line layers defining at least two memory planes.

27. The method of claim 26 wherein the array comprises at least one layer of rail-stack array lines.

28. The method of claim 27 wherein at least one layer of passive element memory cell material is continuous along the selected array line associated with the more lightly-doped side of the memory cell.

29. The method of claim 24 wherein the memory array comprises at least three array line layers defining at least two memory planes, and comprises memory cells whose anode region is alternately an upper region of some memory planes and a lower region of vertically adjacent memory planes.

30. The method of claim 24 wherein:

the more lightly-doped region comprises an n−

region associated with a word line;

the more heavily-doped region comprises a p+ region associated with a bit line;

the word line is pulsed with a negative-going programming pulse to a selected bias voltage for the word line; and

the bit line is pulsed with a positive-going programming pulse to a selected bias voltage for the bit line.

31. The method of claim 30 further comprising programming more than one memory cell associated with a word line by pulsing each of a number of bit lines within a single word line pulse.

32. The method of claim 24 wherein the first time period substantially occurs within the second time period.

33. The method of claim 24 wherein each array line coupled to the more lightly-doped region of memory cells associated therewith comprises a continuous semiconductor layer that forms the more lightly-doped region of each such memory cell associated therewith.

34. The method of claim 24 wherein each array line coupled to the more lightly-doped region of memory cells associated therewith comprises a continuous semiconductor layer that connects to the more lightly-doped region of each such memory cell associated therewith, wherein the continuous semiconductor layer and the more lightly-doped regions of each memory cell have a different doping density.

35. The method of claim 24 wherein each array line coupled to the more lightly-doped region of memory cells associated therewith comprises a rail-stack.

36. The method of claim 24 further comprising:

pulsing for a third time a third selected array line coupled to the more heavily-doped region of a second selected memory cell from an unselected bias voltage to a selected bias voltage, said second selected memory cell also being coupled to the second selected array line;

wherein the third time period substantially occurs within the second time period.

37. The method of claim 36 wherein the first and third pulses overlap.

38. The method of claim 36 wherein the first and third pulses do not substantially overlap.

39. An integrated circuit comprising:

a memory array having at least one memory plane, said array comprising memory cells coupled between an associated one of a respective plurality of array lines on each of two memory array layers, comprising memory cells having an anode region and a cathode region, one of said cathode or anode regions being configured to inject charge to the other region when forward biased; and

array support circuitry configured, when in a programming mode, for driving a first array line associated with the injecting region of a selected memory cell to a selected bias voltage for the first array line, for driving a second array line associated with the non-injecting region of the selected cell to a selected bias voltage for the second array line, and for then driving the first array line to an unselected bias voltage for the first array line, and driving the second array line to an unselected bias voltage for the second array line, wherein the first array line voltage transitions at least a first percentage toward its unselected bias voltage before the second array line transitions at most a second percentage toward its unselected bias voltage.

40. The integrated circuit of claim 39 wherein the memory array comprises a three-dimensional array having at least three array line layers defining at least two memory planes.

41. The integrated circuit of claim 40 wherein the memory array comprises memory cells whose anode region is alternately an upper region of some memory layers and a lower region of vertically adjacent memory layers.

42. The integrated circuit of claim 40 wherein the memory array comprises memory cells whose anode region is either an upper region of all memory layers, or a lower region of all memory layers.

43. The integrated circuit of claim 39 wherein the memory array comprises antifuse memory cells.

44. The integrated circuit of claim 43 wherein the memory array includes memory cells respectively comprising, at least when programmed, a diode having a first semiconductor region of a first conductivity type coupled to a respective one of a plurality of array lines on a first associated array line layer, and having a second semiconductor region of a second conductivity type coupled to a respective one of a plurality of array lines on a second associated array line layer, said second semiconductor region being more lightly doped than the first semiconductor region, said non-injecting region comprising the second semiconductor region, and said injecting region comprising the first semiconductor region.

45. The integrated circuit of claim 44 wherein the second semiconductor region comprises a lightly-doped n-type (n−

) semiconductor region.

46. The integrated circuit of claim 44 wherein the second semiconductor region comprises a lightly-doped p-type (p−

) semiconductor region.

47. The integrated circuit of claim 44 wherein the second semiconductor region is initially formed as an intrinsic region.

48. The integrated circuit of claim 39 wherein the memory array comprises fuse memory cells.

49. The integrated circuit of claim 39 wherein the memory array comprises memory cells including a ferro-electric material.

50. The integrated circuit of claim 39 wherein the memory array comprises memory cells including an organic layer.

51. The integrated circuit of claim 39 wherein said non-injecting regions comprise lightly-doped semiconductor regions, and said injecting regions comprise more heavily doped semiconductor regions.

52. The integrated circuit of claim 39 wherein said non-injecting regions comprise lightly-doped semiconductor regions, and said injecting regions comprise a metal.

53. The integrated circuit of claim 39 wherein:

the first percentage comprises around 50%; and

the second percentage comprises around 50%.

54. The integrated circuit of claim 39 wherein:

the first percentage comprises around 90%; and

the second percentage comprises around 10%.

55. The integrated circuit of claim 39 wherein the second array line voltage transitions at least a third percentage toward its selected bias voltage before the first array line transitions at most a fourth percentage toward its selected bias voltage.

56. The integrated circuit of claim 55 wherein:

the third percentage comprises around 50%; and

the fourth percentage comprises around 50%.

57. The integrated circuit of claim 55 wherein:

the third percentage comprises around 90%; and

the fourth percentage comprises around 10%.

58. The integrated circuit of claim 39 wherein each array line associated with a memory cell non-injecting region comprises a continuous semiconductor layer that forms a portion of the respective non-injecting region of respective memory cells associated therewith.

59. The integrated circuit of claim 39 wherein each array line associated with a memory cell non-injecting region comprises a continuous semiconductor layer that connects to the respective non-injecting region of respective memory cells associated therewith, wherein the continuous semiconductor layer and the non-injecting regions have a different doping density.

60. The integrated circuit of claim 58 wherein the array comprises at least one layer of rail-stack array lines.

61. The integrated circuit of claim 60 wherein the rail-stack array lines include a conductor comprising a metal.

62. A computer readable medium encoding an integrated circuit, said encoded integrated circuit as recited in claim 39.

63. A method for manufacturing an integrated circuit memory device comprising:

providing a programmable memory array of passive element memory cells, each memory cell comprising, at least when programmed, a diode having a first semiconductor region of a first conductivity type coupled to a respective one of a plurality of X-lines, and having a second semiconductor region of a second conductivity type coupled to a respective one of a plurality of Y-lines, said first semiconductor region being more lightly doped than the second semiconductor region, each respective X-line comprising a semiconductor-layer coupled between the respective first semiconductor regions of adjacent memory cells associated with the respective X-line,

providing array support circuitry configured for impressing a programming pulse on a selected X-line and a programming pulse on a first selected Y-line;

wherein the selected X-line is pulsed from an unselected X-line bias voltage to a selected X-line bias voltage, and the first selected Y-line is pulsed from an unselected Y-line bias voltage to a selected Y-line bias voltage; and

wherein the first selected Y-line pulse substantially falls within the selected X-line pulse.

64. The method of claim 63 wherein the programmable memory array comprises antifuse memory cells.