Apparatus and method for disturb-free programming of passive element memory cells
First Claim
1. A method for programming a memory array having at least one memory plane, said array comprising memory cells coupled between an associated one of a respective plurality of array lines on each of two memory array layers, comprising memory cells having an anode region and a cathode region, one of said cathode or anode regions being configured to inject charge to the other region when forward biased, said method comprising:
- driving a first array line associated with the injecting region of a selected memory cell to a selected bias voltage for the first array line; and
driving a second array line associated with the non-injecting region of the selected cell to a selected bias voltage for the second array line;
then driving the first array line to an unselected bias voltage for the first array line; and
driving the second array line to an unselected bias voltage for the second array line, wherein the first array line voltage transitions at least a first percentage toward its unselected bias voltage before the second array line transitions at most a second percentage toward its unselected bias voltage.
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Abstract
In a passive element memory array, such as a rail stack array having a continuous semiconductor region along one or both of the array lines, programming a memory cell may disturb nearby memory cells as result of a leakage path along the array line from the selected cell to the adjacent cell. This effect may be reduced substantially by changing the relative timing of the programming pulses applied to the array lines for the selected memory cell, even if the voltages are unchanged. In an exemplary three-dimensional antifuse memory array, a positive-going programming pulse applied to the anode region of the memory cell preferably is timed to lie within the time that a more lightly-doped cathode region is pulsed low.
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Citations
64 Claims
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1. A method for programming a memory array having at least one memory plane, said array comprising memory cells coupled between an associated one of a respective plurality of array lines on each of two memory array layers, comprising memory cells having an anode region and a cathode region, one of said cathode or anode regions being configured to inject charge to the other region when forward biased, said method comprising:
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driving a first array line associated with the injecting region of a selected memory cell to a selected bias voltage for the first array line; and
driving a second array line associated with the non-injecting region of the selected cell to a selected bias voltage for the second array line;
thendriving the first array line to an unselected bias voltage for the first array line; and
driving the second array line to an unselected bias voltage for the second array line, wherein the first array line voltage transitions at least a first percentage toward its unselected bias voltage before the second array line transitions at most a second percentage toward its unselected bias voltage. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23)
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24. A method for programming a memory array of antifuse memory cells coupled between a respective array line on one memory array layer and a respective array line on another memory array layer, said memory cells comprising two opposite conductivity type semiconductor regions, one being more lightly-doped than the other, said method comprising:
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pulsing for a first time period a first selected array line coupled to the more heavily-doped region of a selected memory cell from an unselected bias voltage to a selected bias voltage; and
pulsing for a second time period a second selected array line coupled to the more lightly-doped region of the selected memory cell from an unselected bias voltage to a selected bias voltage;
wherein the first and second array line pulses are arranged so that the selected memory cell, once programmed, is reversed biased whenever the second selected array line is biased at an intermediate voltage closer to its unselected bias voltage than its selected bias voltage. - View Dependent Claims (25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38)
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39. An integrated circuit comprising:
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a memory array having at least one memory plane, said array comprising memory cells coupled between an associated one of a respective plurality of array lines on each of two memory array layers, comprising memory cells having an anode region and a cathode region, one of said cathode or anode regions being configured to inject charge to the other region when forward biased; and
array support circuitry configured, when in a programming mode, for driving a first array line associated with the injecting region of a selected memory cell to a selected bias voltage for the first array line, for driving a second array line associated with the non-injecting region of the selected cell to a selected bias voltage for the second array line, and for then driving the first array line to an unselected bias voltage for the first array line, and driving the second array line to an unselected bias voltage for the second array line, wherein the first array line voltage transitions at least a first percentage toward its unselected bias voltage before the second array line transitions at most a second percentage toward its unselected bias voltage. - View Dependent Claims (40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62)
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63. A method for manufacturing an integrated circuit memory device comprising:
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providing a programmable memory array of passive element memory cells, each memory cell comprising, at least when programmed, a diode having a first semiconductor region of a first conductivity type coupled to a respective one of a plurality of X-lines, and having a second semiconductor region of a second conductivity type coupled to a respective one of a plurality of Y-lines, said first semiconductor region being more lightly doped than the second semiconductor region, each respective X-line comprising a semiconductor-layer coupled between the respective first semiconductor regions of adjacent memory cells associated with the respective X-line, providing array support circuitry configured for impressing a programming pulse on a selected X-line and a programming pulse on a first selected Y-line;
wherein the selected X-line is pulsed from an unselected X-line bias voltage to a selected X-line bias voltage, and the first selected Y-line is pulsed from an unselected Y-line bias voltage to a selected Y-line bias voltage; and
wherein the first selected Y-line pulse substantially falls within the selected X-line pulse. - View Dependent Claims (64)
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Specification