Signal timing adjustment device, signal timing adjustment system, signal timing adjustment amount setting program, and storage medium storing the program

• US 20040190665A1
• Filed: 03/26/2004
• Published: 09/30/2004
• Est. Priority Date: 03/31/2003
• Status: Active Grant

• Current Assignee: Sharp Kabushiki Kaisha (Hon Hai Precision Industry Co., Ltd.)
• Original Assignee: Sharp Kabushiki Kaisha (Hon Hai Precision Industry Co., Ltd.)
• Inventors: Murakawa, Masahiro, Uratani, Munehiro, Higuchi, Tetsuya, Takahashi, Eiichi, Kasai, Yuji
• Granted Patent: US 7,447,289 B2
• Time in Patent Office: Days
• US Class Current: 375/354
• CPC Class Codes: H03L 7/087 using at least two phase detectors or a frequency and phase detector in the loop
• CPC Class Codes: H04L 7/0337 Selecting between two or more discretely delayed clocks or selecting between two or more discretely delayed received code signals

Abstract

Delay time between an input of data to a circuit block and an output of the data from the data block is measured in accordance with a timing at which the data from the circuit block is acquired by a measurement register and a timing at which the data from the circuit block is acquired by a data latch. An LSI tester sets well voltage adjustment values so that delay time of each circuit block is averaged. From voltages generated by the adjustment voltage generating circuit, a selector selects voltages that are in accordance with the well voltage adjustment values. The voltages selected are applied to a well of a CMOS transistor of each clock timing adjustment circuit. Delay time between timings of inputted clocks is thus adjusted.

Claims

1. A signal timing adjustment device, comprising:

a voltage generating section for generating a plurality of adjustment voltages;

a voltage selecting section for selecting, from the plurality of adjustment voltages, an adjustment voltage that is in accordance with a delay-time adjustment amount, which is set so that delay time of each circuit block in an integrated circuit becomes closer to an average value of the delay time, the delay time being time between an input of data to the circuit block and an output of the data from the circuit block; and

a delay-adjustment section for increasing or decreasing the delay time by using a transistor at which a threshold voltage changes in accordance with a value of the adjustment voltage selected.

2. A signal timing adjustment device as set forth in claim 1, further comprising:

a delay measurement section for measuring the delay time.

3. The signal timing adjustment device as set forth in claim 2, wherein:

the delay measurement section includes

a pulse generating section for generating a pulse in synchronization with a high-speed clock, and shifting a generation timing of the pulse in an increment of one clock of the high-speed clock;

a latch that acquires and holds, in synchronization with a low-speed clock, data supplied from the circuit block; and

a register that acquires and holds, in synchronization with the pulse, the data supplied from the circuit block.

4. The signal timing adjustment device as set forth in claim 1, wherein:

a well of the transistor is separated from a well of another circuit that is formed on a same substrate; and

the adjustment voltage selected is applied to the well of the transistor.

5. The signal timing adjustment device as set forth in claim 1, the signal timing adjustment device being contained in the integrated circuit.

6. A signal timing adjustment device as set forth in claim 5, further comprising:

a fixing section for fixing the delay-time adjustment amount.

7. A signal timing adjustment system, comprising:

a signal timing adjustment device, including

a voltage generating section for generating a plurality of adjustment voltages;

a voltage selecting section for selecting, from the plurality of adjustment voltages, an adjustment voltage that is in accordance with a delay-time adjustment amount, which is set so that delay time of each circuit block in an integrated circuit becomes closer to an average value of the delay time, the delay time being time between an input of data to the circuit block and an output of the data from the circuit block; and

a delay-adjustment section for increasing or decreasing the delay time by using a transistor at which a threshold voltage changes in accordance with a value of the adjustment voltage selected;

a delay measurement section for measuring the delay time;

an average value calculating section for calculating the average value of the delay time, the delay time having been measured by the delay measurement section; and

an adjustment amount setting section for setting the delay-time adjustment amount so that a difference between the delay time and the average value becomes smaller, the average value having been calculated by the average value calculating section.

8. A signal timing adjustment amount setting program for a signal timing adjustment system including

a signal timing adjustment device, including (i) a voltage generating section for generating a plurality of adjustment voltages, (ii) a voltage selecting section for selecting, from the plurality of adjustment voltages, an adjustment voltage that is in accordance with a delay-time adjustment amount, which is set so that delay time of each circuit block in an integrated circuit becomes closer to an average value of the delay time, the delay time being time between an input of data to the circuit block and an output of the data from the circuit block, and (iii) a delay-adjustment section for increasing or decreasing the delay time by using a transistor at which a threshold voltage changes in accordance with a value of the adjustment voltage selected;

a delay measurement section for measuring the delay time;

an average value calculating section for calculating the average value of the delay time, the delay time having been measured by the delay measurement section; and

an adjustment amount setting section for setting the delay-time adjustment amount so that a difference between the delay time and the average value becomes smaller, the average value having been calculated by the average value calculating section,

the signal timing adjustment amount setting program causing a computer to function as the average value calculating section and the adjustment amount setting section.

9. A computer-readable storage medium storing a signal timing adjustment amount setting program for a signal timing adjustment system including

a signal timing adjustment device, including (i) a voltage generating section for generating a plurality of adjustment voltages, (ii) a voltage selecting section for selecting, from the plurality of adjustment voltages, an adjustment voltage that is in accordance with a delay-time adjustment amount, which is set so that delay time of each circuit block in an integrated circuit becomes closer to an average value of the delay time, the delay time being time between an input of data to the circuit block and an output of the data from the circuit block, and (iii) a delay-adjustment section for increasing or decreasing the delay time by using a transistor at which a threshold voltage changes in accordance with a value of the adjustment voltage selected;

a delay measurement section for measuring the delay time;

an average value calculating section for calculating the average value of the delay time, the delay time having been measured by the delay measurement section; and

an adjustment amount setting section for setting the delay-time adjustment amount so that a difference between the delay time and the average value becomes smaller, the average value having been calculated by the average value calculating section,

the signal timing adjustment amount setting program causing a computer to function as the average value calculating section and the adjustment amount setting section.