Wafer scale package and method of assembly

• US 20040191957A1
• Filed: 04/09/2004
• Published: 09/30/2004
• Est. Priority Date: 03/26/2003
• Status: Active Grant

• Current Assignee: Northrop Grumman Systems Corporation (Northrop Grumman Corporation)
• Original Assignee: Northrop Grumman Corporation
• Inventors: Smith, Philip C., Chen, Li-Shu, Fudem, Howard, Moloney, Thomas J.
• Granted Patent: US 6,939,784 B2
• Time in Patent Office: Days
• US Class Current: 438/110
• CPC Class Codes: B81B 2201/018 Switches not provided for in B81B2201/014 - B81B2201/016
• CPC Class Codes: B81B 2207/097 Interconnects arranged on the substrate or the lid, and covered by the package seal
• CPC Class Codes: B81C 1/00301 Connecting electric signal lines from the MEMS device with external electrical signal lines, e.g. through vias
• CPC Class Codes: B81C 2203/0118 Bonding a wafer on the substrate, i.e. where the cap consists of another wafer
• CPC Class Codes: H01L 21/50 Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
• CPC Class Codes: H01L 23/10 characterised by the material or arrangement of seals between parts, e.g. between cap and base of the container or between leads and walls of the container
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 2924/01079 Gold [Au]
• CPC Class Codes: H01L 2924/3011 Impedance

Abstract

A plurality of electronic circuits and associated signal lines are positioned at respective locations on a base wafer. A cover wafer, which fits over the base wafer, includes a corresponding like number of locations each including one or more cavities to accommodate the electronic circuit and associated signal lines. The cover wafer includes a plurality of vias for making electrical connection to the signal lines. A multi layer metallic arrangement hermetically seals the periphery of each location as well as sealing the bottom of each via. The joined base and cover wafers may then be diced to form individual die packages.

Claims

1. A method of making a wafer scale package for electronic circuits, comprising the steps of:

placing electronic circuits each having at least one electronic device and associated signal lines at respective locations on a base wafer;

forming cavities on the undersurface of a cover wafer at respective locations to accommodate said respective electronic devices, when said wafers are joined;

forming and metalizing vias in said cover wafer;

metalizing the periphery of each said location on said base and cover wafers;

metalizing an electric contact between the bottom of a said metalized via and said signal lines;

joining said base and cover wafers at predetermined pressure, temperature and time conditions to form a peripheral hermetic seal around each said location and a via hermetic seal around each said bottom of a said via; and

dicing said joined and sealed wafers along said locations to provide individual die packages.

2. A method of making a wafer scale package according to claim 1 which includes the step of:

providing a base wafer of quartz.

3. A method of making a wafer scale package according to claim 1 which includes the step of:

providing a cover wafer of quartz.

4. A method of making a wafer scale package according to claim 1 which includes the step of:

metalizing the periphery of each said location on said base and cover wafers with a plurality of metal layers which include indium and nickel.

5. A method of making a wafer scale package according to claim 1 which includes the step of:

applying an initial metal layer of titanium on the top surface of said base wafer around the periphery of each said location; and

applying an initial metal layer of titanium on the undersurface of said cover wafer around the periphery of each said location.

6. A method of making a wafer scale package according to claim 1 which includes the step of:

joining said base and cover wafers at a pressure of around 30 to 80 psi.

7. A method of making a wafer scale package according to claim 1 which includes the step of:

joining said base and cover wafers at a temperature of around 120°

C. to 200°

C.

8. A method of making a wafer scale package according to claim 1 which includes the step of:

joining said base and cover wafers at said predetermined pressure and temperature for around 1 to 3 hours.