Adjusting the strength of output buffers

• US 20040191976A1
• Filed: 03/27/2003
• Published: 09/30/2004
• Est. Priority Date: 03/27/2003
• Status: Active Grant

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Udupa, Anand Hariraj, Appala, Visvesvaraya Pentakota
• Granted Patent: US 6,985,006 B2
• Time in Patent Office: Days
• US Class Current: 438/200
• CPC Class Codes: H03K 19/00361 in field effect transistor circuits

Abstract

The rate at which the output of an output buffer changes is determined, and the strength of the output buffer is modified until the rate of change reaches a desired rate. The desired rate may be selected such that strength of the output buffer matches the then existing load. In other words, the strength may be only as much as needed to drive the then existing load. As a result, effects such as switching noise may be considerably reduced.

Claims

1. A method of adjusting a strength of an output buffer driving a load, said method comprising:

determining a rate at which an output of said output buffer changes in response to receiving a transition on an input of said output buffer; and

changing said strength of said output buffer until said rate equals a desired rate in response to receiving additional transitions on said input.

2. The method of claim 1, wherein said transition comprises either from logical 0 to logical 1 or from logical 1 to logical 0.

3. The method of claim 2, wherein said output buffer comprises a plurality of inverters connected in parallel, wherein each of said plurality of inverters comprises a PMOS transistor and a NMOS transistor, wherein said changing comprises:

determining a first set of PMOS transistors which are to be enabled to achieve said desired rate when said transition is from logical 0 to logical 1, wherein said first set of PMOS transistors being comprised in said plurality of inverters;

determining a first set of NMOS transistors which are to be enabled to achieve said desired rate when said transition is from logical 1 to logical 0, wherein said first set of NMOS transistors being comprised in said plurality of inverters; and

enabling said first set of PMOS transistors and said first set of NMOS transistors, wherein said enabling causes a W/L to be controlled to achieve said desired rate with respect to both of said logical 1 to logical 0, and logical 0 to logical 1 transitions.

4. The method of claim 2, wherein said output buffer comprises a PMOS transistor and a NMOS transistor, wherein said changing comprises:

modifying a V_GS voltage associated with said PMOS transistor to control said desired rate with respect to said transition from logical 0 to logical 1; and

modifying a V_GS voltage associated with said NMOS transistor to control said desired rate with respect to said transition from logical 1 to logical 0.

5. The method of claim 2, wherein said determining comprises:

storing a previous value received by said output buffer;

comparing said previous value to a present value to determine whether said transition has occurred; and

comparing a voltage level on said output with a threshold voltage at a time point after a delay elapses in relation to a clock signal used to control said output buffer.

6. The method of claim 5, wherein said threshold voltage comprises a high voltage level when measuring said rate with reference to transition from logical 0 to logical 1, and a low voltage level when measuring said rate with reference to transition from logical 1 to 0.

7. An integrated circuit comprising:

an output buffer to receive an input transition on an input path and to generate an output transition on an output path in response, said output buffer driving a load coupled to said output path; and

a strength controller determining a rate at which said output transition changes on said output path, and changing a strength of said output buffer until said rate equals a desired rate in response to receiving additional transitions on said input path.

8. The integrated circuit of claim 7, wherein said output transition comprises either from logical 0 to logical 1 or from logical 1 to logical 0.

9. The integrated circuit of claim 8, wherein said output buffer comprises a plurality of inverters connected in parallel, wherein each of said plurality of inverters comprises a PMOS transistor and a NMOS transistor, said each of said plurality of inverters further comprising:

a first switch between a source terminal and a gate terminal of said PMOS transistor;

a second switch between said input path and said gate terminal of said PMOS transistor;

a third switch between a source terminal and a gate terminal of said NMOS transistor; and

a fourth switch between said input path and said gate terminal of said NMOS transistor.

10. The integrated circuit of claim 9, wherein said strength controller comprises a control block enabling a first set of PMOS transistors by controlling corresponding ones of said first switch to achieve said desired rate when said output transition is from logical 0 to logical 1, wherein said first set of PMOS transistors are comprised in said plurality of inverters;

said control block further enabling a first set of NMOS transistors by controlling corresponding ones of said third switch to achieve said desired rate when said output transition is from logical 1 to logical 0, wherein said first set of NMOS transistors being comprised in said plurality of inverters,

wherein enabling said first set of PMOS transistors and said first set of NMOS transistors causes a W/L to be controlled to achieve said desired rate with respect to both of said logical 1 to logical 0, and said logical 0 to logical 1 transitions.

11. The integrated circuit of claim 8, wherein said output buffer comprises a PMOS transistor and a NMOS transistor, wherein said strength controller comprises a control block modifying a V_GS voltage associated with said PMOS transistor to control said desired rate with respect to transition from logical 0 to logical 1, and modifying a V_GS voltage associated with said NMOS transistor to control said desired rate with respect to transition from logical 1 to logical 0.

12. The integrated circuit of claim 8, wherein said strength controller storing a previous value received by said output buffer and compares said previous value to a present value to determine whether said input transition has occurred, said strength controller comparing a voltage level on said output path with a threshold voltage at a time point after a delay elapses in relation to a clock signal used to control said output buffer.

13. The integrated circuit of claim 12, wherein said threshold voltage comprises a high voltage level when measuring said rate with reference to transition from logical 0 to logical 1, and a low voltage level when measuring said rate with reference to transition from logical 1 to 0.

14. An apparatus for adjusting a strength of an output buffer driving a load, said apparatus comprising:

means for determining a rate at which an output of said output buffer changes in response to receiving a transition on an input of said output buffer; and

means for changing said strength of said output buffer until said rate equals a desired rate in response to receiving additional transitions on said input.

15. The apparatus of claim 14, wherein said transition comprises either from logical 0 to logical 1 or from logical 1 to logical 0.

16. The apparatus of claim 15, wherein said output buffer comprises a plurality of inverters connected in parallel, wherein each of said plurality of inverters comprises a PMOS transistor and a NMOS transistor, wherein said means for changing comprises:

means for determining a first set of PMOS transistors which are to be enabled to achieve said desired rate when said transition is from logical 0 to logical 1, wherein said first set of PMOS transistors being comprised in said plurality of inverters;

means for determining a first set of NMOS transistors which are to be enabled to achieve said desired rate when said transition is from logical 1 to logical 0, wherein said first set of NMOS transistors being comprised in said plurality of inverters; and

means for enabling said first set of PMOS transistors and said first set of NMOS transistors, wherein said means for enabling causes a W/L to be controlled to achieve said desired rate with respect to both of said logical 1 to logical 0, and logical 0 to logical 1 transitions.

17. The apparatus of claim 15, wherein said output buffer comprises a PMOS transistor and a NMOS transistor, wherein said means for changing comprises:

means for modifying a V_GS voltage associated with said PMOS transistor to control said desired rate with respect to said transition from logical 0 to logical 1; and

means for modifying a V_GS voltage associated with said NMOS transistor to control said desired rate with respect to said transition from logical 1 to logical 0.

18. The apparatus of claim 15, wherein said means for determining comprises:

means for storing a previous value received by said output buffer;

means for comparing said previous value to a present value to determine whether said transition has occurred; and

means for comparing a voltage level on said output with a threshold voltage at a time point after a delay elapses in relation to a clock signal used to control said output buffer.

19. The apparatus of claim 18, wherein said threshold voltage comprises a high voltage level when measuring said rate with reference to transition from logical 0 to logical 1, and a low voltage level when measuring said rate with reference to transition from logical 1 to 0.

20. A device comprising:

a data source providing a sequence of digital values;

an output buffer coupled to said data source to receive said sequence of digital values on an input path, said sequence of digital values including an input transition, said output buffer generating an output transition on an output path in response to said input transition, said output buffer driving a load coupled to said output path; and

a strength controller determining a rate at which said output transition changes on said output path, and changing a strength of said output buffer until said rate equals a desired rate in response to receiving additional transitions on said input path, said additional transitions also being contained in said sequence of digital values.

21. The device of claim 20, wherein said output transition comprises either from logical 0 to logical 1 or from logical 1 to logical 0.

22. The device of claim 21, wherein said output buffer comprises a plurality of inverters connected in parallel, wherein each of said plurality of inverters comprises a PMOS transistor and a NMOS transistor, said each of said plurality of inverters further comprising:

a first switch between a source terminal and a gate terminal of said PMOS transistor;

a second switch between said input path and said gate terminal of said PMOS transistor;

a third switch between a source terminal and a gate terminal of said NMOS transistor; and

a fourth switch between said input path and said gate terminal of said NMOS transistor.

23. The device of claim 22, wherein said strength controller comprises a control block enabling a first set of PMOS transistors by controlling corresponding ones of said first switch to achieve said desired rate when said output transition is from logical 0 to logical 1, wherein said first set of PMOS transistors are comprised in said plurality of inverters;

said control block further enabling a first set of NMOS transistors by controlling corresponding ones of said third switch to achieve said desired rate when said output transition is from logical 1 to logical 0, wherein said first set of NMOS transistors being comprised in said plurality of inverters,

wherein enabling said first set of PMOS transistors and said first set of NMOS transistors causes a W/L to be controlled to achieve said desired rate with respect to both of said logical 1 to logical 0, and said logical 0 to logical 1 transitions.

24. The device of claim 21, wherein said output buffer comprises a PMOS transistor and a NMOS transistor, wherein said strength controller comprises a control block modifying a V_GS voltage associated with said PMOS transistor to control said desired rate with respect to transition from logical 0 to logical 1, and modifying a V_GS voltage associated with said NMOS transistor to control said desired rate with respect to transition from logical 1 to logical 0.

25. The device of claim 21, wherein said strength controller storing a previous value received by said output buffer from said data source and compares said previous value to a present value to determine whether said input transition has occurred, said strength controller comparing a voltage level on said output path with a threshold voltage at a time point after a delay elapses in relation to a clock signal used to control said output buffer.

26. The device of claim 25, wherein said threshold voltage comprises a high voltage level when measuring said rate with reference to transition from logical 0 to logical 1, and a low voltage level when measuring said rate with reference to transition from logical 1 to 0.

27. The device of claim 26, further comprising:

a lens through which a light from an image is passed;

a charge coupled device (CCD) generating a plurality of voltage values in response to incidence of said light;

an analog front end (AFE) converting said plurality of voltage values to generate said sequence of digital values, wherein said AFE comprises said data source; and

said load coupled to said output path comprises one of a computer system, a floppy disk, a printer and a video player.

28. The invention of claim 27, wherein said device comprises a digital camera or a scanner.