Pseudo-random number generator

• US 20040193664A1
• Filed: 03/25/2004
• Published: 09/30/2004
• Est. Priority Date: 03/31/2003
• Status: Active Grant

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: NEC Electronics Corporation (Renesas Electronics Corporation)
• Inventors: Shimasaki, Shinya
• Granted Patent: US 7,376,687 B2
• Time in Patent Office: Days
• US Class Current: 708/252
• CPC Class Codes: G06F 7/582 Pseudo-random number generators

Abstract

A pseudo-random number generator comprises a linear feedback register for generating pseudo-random numbers; and a signal generator for generating a shift clock for operating a linear feedback register and predetermined input data. The linear feedback register has a plurality of registers connected in series, a first logical operation circuit for taking logical operation of output data from predetermined registers to deliver the result thereof, and a second logical operation circuit for taking logical operation of input data supplied from the outside and output data of the first logical operation circuit to supply the result thereof to any one of the registers.

Claims

1. A pseudo-random number generator comprising:

a linear feedback register including a plurality of registers connected in series, a first logical operation circuit for taking logical operation of output data from the predetermined registers to deliver the result of the logical operation, and a second logical operation circuit for taking logical operation of input data supplied from the outside and output data of said first logical operation circuit to supply any one of said plurality of registers with the result of the logical operation, said linear feedback register generating pseudo-random numbers from said registers; and

a signal generator for generating a shift clock for operating said linear feedback register, and for generating said input data using a first clock at a constant period and a second clock synchronized to said first clock.

2. The pseudo-random number generator according to claim 1, further comprising:

an oscillator for generating a third clock which is unstable in frequency; and

a Pre-SEED generator circuit for supplying said linear feedback register with said shift clock which is generated by taking logical operation of said third clock and a fourth clock asynchronous to said third clock, and for supplying said linear feedback register with said input data which comprises said fourth clock.

3. The pseudo-random number generator according to claim 1, wherein:

said signal generator delivers said shift clock which is one of said first clock and a clock generated by dividing said first clock, said first clock and said divided clock being switched at predetermined intervals.

4. The pseudo-random number generator according to claim 1, further comprising:

an access controller for reading a random number generated by said linear feedback register at a cycle different from the period of said shift clock.

5. The pseudo-random number generator according to claim 1, further comprising:

a write circuit for providing logical operation of output data from said linear feedback register and arbitrary data entered from the outside,

wherein said linear feedback register rewrites an initial value into said registers with data delivered from said write circuit.

6. The pseudo-random number generator according to claim 1, wherein said linear feedback register comprises a number of registers larger than the number of bits of said random number.