Bi-quad digital filter configured with a bit binary rate multiplier
First Claim
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1. A bi-quad filter circuit, comprising:
- an input for receiving an input signal;
at least one binary rate multiplier (BRM) configured to receive and convert the input signal to a binary rate signal; and
an output for outputting the binary rate signal.
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Abstract
The invention is directed to a bi-quad filter circuit configured with sigma-delta devices that operate as binary rate multipliers (BRMs). Unlike conventional bi-quad filter circuits, the invention provides a bi-quad filter configured with a single-bit BRM. In another embodiment, the invention further provides a bi-quad filter configured with multiple-bit BRMs.
20 Citations
11 Claims
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1. A bi-quad filter circuit, comprising:
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an input for receiving an input signal;
at least one binary rate multiplier (BRM) configured to receive and convert the input signal to a binary rate signal; and
an output for outputting the binary rate signal. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 10)
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9. A bi-quad filter circuit, comprising:
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an input for receiving an input signal;
at least one binary rate multiplier (BRM) configured to receive and convert a digital signal to a binary rate signal;
a plurality of integrators configured in at least one feed back loop to produce a filtered digital signal, wherein each input to each integrator is received by a BRM; and
an output for outputting the binary rate signal.
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11. A multiple bit BRM, comprising:
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an input configured to receive a digital input signal;
an output configured to output a binary rate signal;
a first adder configured to receive a first portion of bits from the input signal, to add two signals, and to output a sum output signal and a carry output signal;
a flip flop circuit configured to output a toggle output in response to receiving a sum signal from the first adder, wherein the first adder is further configured to add the toggle output with the first portion of the input signal; and
a second adder configured to add the carry output signal from the first adder to a second portion of the input signal and to output the binary rate signal.
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Specification