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Bi-quad digital filter configured with a bit binary rate multiplier

  • US 20040193665A1
  • Filed: 06/02/2003
  • Published: 09/30/2004
  • Est. Priority Date: 03/28/2003
  • Status: Active Grant
First Claim
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1. A bi-quad filter circuit, comprising:

  • an input for receiving an input signal;

    at least one binary rate multiplier (BRM) configured to receive and convert the input signal to a binary rate signal; and

    an output for outputting the binary rate signal.

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