Priority circuit for content addressable memory
First Claim
1. A digital signal processor, comprising:
- a content addressable memory (CAM) array having a plurality of rows of CAM cells;
an array of storage elements having a plurality of rows of the storage elements coupled to the CAM array, each row of storage elements to store a number corresponding to a data word stored in one of the rows of the CAM cells; and
priority logic coupled to the array of storage elements, the priority logic to provide to a plurality of priority signal lines an indication of a location of a particular number in the array of storage elements, wherein the priority logic comprises;
a first plurality of compare circuits, each compare circuit coupled to one of the storage elements in the array of storage elements, and each compare circuit having a first input coupled to a storage element, a second input coupled to a match line, and an input/output line coupled to one of the plurality of priority signal lines; and
a delay circuit coupled to each of the first plurality of compare circuits.
12 Assignments
0 Petitions
Accused Products
Abstract
A digital signal processor having priority logic coupled to an array of storage elements, the priority logic to provide to a priority signal lines an indication of a location of a particular number in the array of storage elements. The priority logic includes compare circuits where each compare circuit is coupled to one of the storage elements in the array of storage elements. Each compare circuit has a first input coupled to a storage element, a second input coupled to a match line, and an input/output line coupled to one of the priority signal lines. The priority logic also includes a delay circuit coupled to each of the compare circuits.
136 Citations
19 Claims
-
1. A digital signal processor, comprising:
-
a content addressable memory (CAM) array having a plurality of rows of CAM cells;
an array of storage elements having a plurality of rows of the storage elements coupled to the CAM array, each row of storage elements to store a number corresponding to a data word stored in one of the rows of the CAM cells; and
priority logic coupled to the array of storage elements, the priority logic to provide to a plurality of priority signal lines an indication of a location of a particular number in the array of storage elements, wherein the priority logic comprises;
a first plurality of compare circuits, each compare circuit coupled to one of the storage elements in the array of storage elements, and each compare circuit having a first input coupled to a storage element, a second input coupled to a match line, and an input/output line coupled to one of the plurality of priority signal lines; and
a delay circuit coupled to each of the first plurality of compare circuits. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15)
-
-
16. A method of operating a digital signal processor, comprising:
-
resolving a priority line coupled to a first column of compare circuits; and
concurrently, de-asserting a match line in the first column of compare circuits and resolving a next priority line coupled to a second column of compare circuits. - View Dependent Claims (17, 19)
-
-
18. A digital signal processor, comprising:
-
means for resolving a priority line coupled to a first column of compare circuits; and
means for concurrently, de-asserting a match line in the first column of compare circuits and resolving a next priority line coupled to a second column of compare circuits.
-
Specification