Physical mode addressing

• US 20040193833A1
• Filed: 03/27/2003
• Published: 09/30/2004
• Est. Priority Date: 03/27/2003
• Status: Abandoned Application

• Current Assignee: Hewlett-Packard Development Company, L.P. (HP Inc.)
• Original Assignee: Hewlett-Packard Development Company, L.P. (HP Inc.)
• Inventors: Garcia, David J., Culley, Paul R., Hilland, Jeffrey, Hampton, Kathryn
• Application Number:
  US10/401,232
• Publication Number:
  US 20040193833A1
• Time in Patent Office: Days
• US Class Current: 711/206
• CPC Class Codes: G06F 12/1072 Decentralised address translation, e.g. in distributed shared memory systems

Abstract

The disclosed embodiments may relate to an address translation mechanism that may include a request that corresponds to a memory access operation. The request may include an address mode field. The address translation mechanism may also include an address field that may be used as a virtual address or a physical address depending on the contents of the address mode field.

Claims

1. An address translation mechanism, comprising:

a request that corresponds to a memory access operation, the request including an address mode field; and

an address field that may be used as a virtual address or a physical address depending on the contents of the address mode field.

2. The address translation mechanism set forth in claim 1, wherein the address mode field is used to specify a steering tag (“

STag”

).

3. The address translation mechanism set forth in claim 1, wherein the address mode field is used to specify information about the memory access operation.

4. The address translation mechanism set forth in claim 1, wherein the address mode field is interpreted as a steering tag (“

STag”

) that identifies a region of memory unless a value in the address mode field corresponds to a predetermined value.

5. The address translation mechanism set forth in claim 1, wherein the address field is interpreted as a physical address if the address mode field corresponds to a predetermined value.

6. The address translation mechanism set forth in claim 1, wherein the request and a memory translation and protection table are used to relate the request to a section of memory if the address mode field does not correspond to a predetermined value.

7. The address translation mechanism set forth in claim 1, wherein the memory access operation is associated with a queue pair that has a queue pair context, the queue pair context including access validation data.

8. The address translation mechanism set forth in claim 1, wherein the request is a work request.

9. The address translation mechanism set forth in claim 1, wherein the request is an incoming remote direct memory access request.

10. A computer network, comprising:

a plurality of computer systems;

at least one input/output device;

a switch network that connects the plurality of computer systems and the at least one input/output device for communication; and

wherein the plurality of computer systems and the at least one input/output device comprises an address translation mechanism, the address translation mechanism comprising;

a request that corresponds to a memory access operation, the request including an address mode field; and

an address field that may be used as a virtual address or a physical address depending on the contents of the address mode field.

11. The computer network set forth in claim 10, wherein the address mode field is used to specify a steering tag (“

STag”

).

12. The computer network set forth in claim 10, wherein the address mode field is used to specify information about the memory access operation.

13. The computer network set forth in claim 10, wherein the address mode field is interpreted as a steering tag (“

STag”

) that identifies a region of memory unless a value in the address mode field corresponds to a predetermined value.

14. The computer network set forth in claim 10, wherein the address field is interpreted as a physical address if the address mode field corresponds to a predetermined value.

15. The computer network set forth in claim 10, wherein the request and a memory translation and protection table are used to relate the request to a section of memory if the address mode field does not correspond to a predetermined value.

16. The computer network set forth in claim 10, wherein the memory access operation is associated with a queue pair that has a queue pair context, the queue pair context including access validation data.

17. The computer network set forth in claim 10, wherein the request is a work request.

18. The computer network set forth in claim 10, wherein the request is an incoming remote direct memory access request.

19. A method of addressing memory locations in a computer system, the method comprising:

processing a request that corresponds to a memory access operation, the request including an address mode field;

evaluating the address mode field;

using an address field as a physical address if the address mode field corresponds to a predetermined value;

using the address field as a virtual address if the address mode field does not correspond to a predetermined value.

20. The method set forth in claim 19, comprising including a steering tag (“

STag”

) as at least a portion of the address mode field.

21. The method set forth in claim 19, comprising using the address mode field to specify information about the memory access operation.

22. The method set forth in claim 19, comprising interpreting the address mode field as a steering tag (“

STag”

) that identifies a region of memory unless a value in the address mode field corresponds to a predetermined value.

23. The method set forth in claim 19, comprising interpreting the address mode field as a physical address if the address mode field corresponds to a predetermined value.

24. The method set forth in claim 19, comprising using the request and a memory translation and protection table to relate the request to a section of memory if the address mode field does not correspond to a predetermined value.

25. The method set forth in claim 19, comprising:

creating a queue pair;

creating a queue pair context that includes access validation data;

comparing the access validation data to the request to determine if the memory access operation is valid.

26. The method set forth in claim 25, comprising:

performing the memory access operation if the comparison if the memory access operation is valid.