System and method for early branch prediction

• US 20040193843A1
• Filed: 03/31/2003
• Published: 09/30/2004
• Est. Priority Date: 03/31/2003
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Valentine, Robert, Lempel, Oded, Kacevas, Nicolas, Altshuler, Eran
• Granted Patent: US 7,174,444 B2
• Time in Patent Office: Days
• US Class Current: 712/207
• CPC Class Codes: G06F 9/3844 using dynamic branch prediction, e.g. using branch history tables

Abstract

A system and method of early branch prediction in a processor to evaluate, typically before a full branch prediction is made, ways in a branch target buffer to determine if any of said ways corresponds to a valid unconditional branch, and upon such determination, to generate a signal to prevent a read of a next sequential chunk.

Claims

1. A method comprising:

preventing a read of a next sequential chunk during branch prediction of a subject chunk.

2. A method as in claim 1, wherein said preventing is conditioned on detecting a valid unconditional branch in said subject chunk.

3. A method as in claim 1, wherein said preventing is conditioned on detecting zero as an offset of a current instruction pointer.

4. A method as in claim 1, comprising determining if at least one way in a branch target buffer corresponds to a valid unconditional branch.

5. A method as in claim 1, comprising detecting if an offset of a way wherein is detected an unconditional branch is greater than an offset of a current instruction pointer.

6. A method as in claim 4, wherein said determining is performed on all ways in said branch target buffer.

7. A method as in claim 4 wherein said determining is performed in a single cycle.

8. A method as in claim 4, wherein said determining if at least one way in said branch target buffer corresponds to a valid unconditional branch includes at least detecting if said way indicates validity in a valid field of said way, unconditional in a branch field of said way and a match in a tag field of said way.

9. A method as in claim 6, wherein said determining is performed on ways in said target branch buffer simultaneously.

10. A method as in claim 1, wherein said preventing is performed while said subject chunk is in a first stage of a branch prediction unit.

11. A method as in claim 1 wherein said preventing is performed before said next sequential chunk is read into a branch prediction unit.

12. A method as in claim 1, wherein said preventing includes at least throttling a clock of a processor.

13. A method of branch prediction, the method comprising evaluating a plurality of ways in a branch target buffer to determine if at least one of said ways corresponds to a valid unconditional branch.

14. A method as in claim 13, wherein said determining includes at least evaluating if one or more of said ways includes at least a valid field indicating validity, a tag field indicating a match and a branch type indicating unconditional.

15. A method as in claim 13, comprising performing said evaluation on each way of said branch target buffer.

16. A method as in claim 13, comprising detecting an offset of 0 in a current instruction pointer.

17. A method as in claim 13, including preventing a read of a next sequential chunk if at least one of said ways corresponds to a valid unconditional branch.

18. A method as in claim 17 wherein said preventing includes at least throttling a clock of said processor.

19. A method as in claim 13, wherein said determining includes at least evaluating if an offset of said ways are greater than or equal to an offset of a current instruction pointer.

20. A system comprising an auxiliary branch prediction circuit to generate a signal to prevent a read of a next sequential chunk.

21. A system as in claim 20, said auxiliary branch prediction circuit to determine if at least one way in a branch target buffer corresponds to a valid unconditional branch.

22. A system as in claim 20, said auxiliary branch prediction circuit to detect zero as an offset of a current instruction pointer.

23. A system as in claim 20, said auxiliary branch prediction circuit to determine and generate said signal within a single cycle.

24. A system as in claim 20, said auxiliary branch prediction circuit to evaluate if one or more of said ways includes at least a valid field indicating validity, a tag field indicating a match and a branch type indicating unconditional.

25. A system as in claim 20, said auxiliary branch prediction circuit to determine if an offset of said way is greater than an offset of a current instruction pointer.

26. A computer system comprising:

an input/output unit; and

a processor including a system for branch prediction, said system including at least a branch prediction circuit to evaluate, in a single cycle, at least one way in a branch target buffer in order to determine if said way corresponds to a valid unconditional branch, and in order to prevent a read of a next sequential chunk.

27. A computer system as in claim 26, wherein said branch prediction unit is to detect if an offset of a current instruction pointer is zero.