Program-controlled unit

• US 20040193853A1
• Filed: 04/23/2004
• Published: 09/30/2004
• Est. Priority Date: 04/20/2001
• Status: Abandoned Application

• Current Assignee: Infineon Technologies AG
• Original Assignee: Infineon Technologies AG
• Inventors: Kolof, Andreas, Maier, Klaus D., Mayer, Albrecht, Konig, Dietmar
• Application Number:
  US10/475,599
• Publication Number:
  US 20040193853A1
• Time in Patent Office: Days
• US Class Current: 712/227
• CPC Class Codes: G06F 11/364 tracing values on a bus
• CPC Class Codes: G06F 11/3648 using additional hardware

Abstract

A program-controlled unit (e.g., a microprocessor) including one or more cores and one or more peripheral component circuits connected to buses (conductive lines), and also including debug resources coupled to the buses for monitoring the transmission of trace information (e.g., selected addresses, data and/or control signals), for generating corresponding signals (e.g., the actual trace information or associated identification codes) that are output from the program-controlled unit or stored in it.

Claims

1. A program-controlled unit having one or more cores (C1, C2), and having debug resources (DR1-DR5), by means of which trace information comprising selected addresses, data and/or control signals is output from the program-controlled unit or stored in it, characterized in that the debug resources (DR1-DR5) comprise one or more components (DR3-DR5) which are connected to lines (BUS1-BUS3) running between the cores (C1, C2) and/or individual components, a plurality of components or all the other components (P1-P3, S1-S3) of the program-controlled unit and which can output, from the program-controlled unit, addresses, data and/or control signals selected from the addresses, data and/or control signals transferred via these lines, or store them in it.

2. The program-controlled unit as claimed in claim 1, characterized in that the components (DR3-DR5) of the debug resources (DR1-DR5) which are connected to the lines (BUS1-BUS3) running between the cores (C1, C2) and/or individual components, a plurality of components or all the other components (P1-P3, S1-S3) of the program-controlled unit can be checked to determine whether the addresses, data and/or control signals transferred via the lines fulfill certain conditions.

3. The program-controlled unit as claimed in claim 1 or 2, characterized in that the components (DR3-DR5) of the debug resources (DR1-DR5) which are connected to the lines (BUS1-BUS3) running between the cores (C1, C2) and/or individual components, a plurality of components or all the other components (P1-P3, S1-S3) of the program-controlled unit can determine whether, and if so which, of the addresses, data and/or control signals which are transferred via the lines are to be output from the program-controlled unit or stored in it.

4. The program-controlled unit as claimed in one of the preceding claims, characterized in that the components (DR3-DR5) of the debug resources (DR1-DR5) which are connected to the lines (BUS1-BUS3) running between the cores (C1, C2) and/or individual components, a plurality of components or all the other components (P1-P3, S1-S3) of the program-controlled unit can cause addresses, data and/or control signals transferred via the lines to be output from the program-controlled unit or stored in it.

5. The program-controlled unit as claimed in one of the preceding claims, characterized in that the debug resources (DR1-DR5) comprise further components (DR1, DR2), these further components (DR1, DR2) being connected to the cores (C1, C2), and these further components examining and influencing selected states or processes in the cores and/or outputting data representing these states or processes from the program-controlled unit or storing it in it.

6. The program-controlled unit as claimed in claim 5, characterized in that the selected states and processes are states and processes from which it is possible to determine which instructions the cores (C1, C2) are carrying out at a particular time.

7. The program-controlled unit as claimed in claim 5 or 6, characterized in that the selected states or processes are exclusively states and processes from which it is possible to determine which instructions the cores (C1, C2) are carrying out at a particular time.

8. The program-controlled unit as claimed in one of the preceding claims, characterized in that the debug resources (DR1-DR5) comprise components, these components being connected to the other components (P1-P3, S1-S3) of the program-controlled unit, and these debug resource components examining and influencing selected states and processes in the other components of the program-controlled unit and/or outputting data representing these states or processes from the program-controlled unit or storing it in it.