Multi-threaded time processing unit for telecommunication systems

• US 20040194109A1
• Filed: 03/25/2003
• Published: 09/30/2004
• Est. Priority Date: 03/25/2003
• Status: Abandoned Application

• Current Assignee: ArrayComm LLC (Ygomi LLC)
• Original Assignee: ArrayComm LLC (Ygomi LLC)
• Inventors: Dahlby, Doug, Chrabieh, Rabih, Boros, Tibor
• Application Number:
  US10/397,689
• Publication Number:
  US 20040194109A1
• Time in Patent Office: Days
• US Class Current: 718/107
• CPC Class Codes: G06F 9/30101 Special purpose registers
• CPC Class Codes: G06F 9/3851 from multiple instruction streams, e.g. multistreaming

Abstract

Embodiments of the invention provide methods and apparatuses to provide concurrent execution of multiple instruction threads for independent control of two or more subsystems of a communication device. One embodiment includes a memory containing a plurality of instruction threads. Each of the plurality of instruction threads contains a timing specification and a corresponding timing reference. An execution unit is coupled to the memory. The execution unit concurrently executes each of the plurality of instruction threads in accordance with the timing specification and the corresponding timing reference of each instruction thread.

Claims

1. A time processing unit for a communication device comprising:

one or more memory devices containing a plurality of instruction threads, wherein each instruction thread contains a timing specification, each instruction thread having a corresponding timing reference; and

one or more instruction execution units, coupled to the one or more memory devices, to concurrently execute each of the plurality of instruction threads in accordance with the corresponding timing reference of each instruction thread, such that the execution of each of the plurality of instruction threads generates control signals at specified times independently for a corresponding subsystem of the communication device.

2. The time processing unit of claim 1 wherein each time reference corresponding to an instruction thread is obtained by combining a common time reference with a timing offset specific to each instruction thread.

3. The time processing unit of claim 2 wherein each timing offset is stored in a separate timing offset register.

4. The time processing unit of claim 2 further comprising:

an external data interface coupling an external entity to the time processing unit to allow the external entity to communicate with the time processing unit.

5. The time processing unit of claim 4 wherein the external data interface is coupled to each separate timing offset register such that each timing offset can be adjusted independently by the external device.

6. The time processing unit of claim 4 wherein the one or more memory devices are coupled to the external data interface such that the plurality of instruction threads and the timing specifications can be loaded into the one or more memory devices.

7. The time processing unit of claim 3 further comprising a plurality of shadow timing offset registers, each shadow timing offset register corresponding to a timing offset register such that the timing offset of each timing offset register is buffered in the corresponding shadow timing offset register.

8. The time processing unit of claim 7 wherein each instruction thread contains a dedicated instruction such that execution of the dedicated instruction causes the timing offset of the corresponding timing offset register to be buffered in the corresponding shadow timing offset register.

9. The time processing unit of claim 1 wherein each of the plurality of instruction threads has a corresponding program counter coupled to one of the one or more instruction execution units such that the one instruction execution unit obtains an address for each instruction of an instruction thread from the corresponding program counter.

10. The time processing unit of claim 9 wherein each program counter has a distinct reset value, each reset value indicating a memory location entry point to the corresponding instruction thread.

11. The time processing unit of claim 10 wherein each distinct memory location entry point contains a jump instruction to direct the one instruction execution unit to a specified memory location containing the instruction thread corresponding to the program counter.

12. The time processing unit of claim 1 wherein the communication device is a user terminal of a telecommunications system and the plurality of corresponding subsystems of the device include a user terminal receiver and a user terminal transmitter.

13. The time processing unit of claim 12 wherein the telecommunications system is a time division duplex telecommunications system.

14. The time processing unit of claim 13 wherein the timing offset of the instruction thread corresponding to the user terminal transmitter and the timing offset of the instruction thread corresponding to the user terminal receiver are adjusted by different values, thereby effecting a transmission timing advance.

15. A method comprising:

generating a first set of control signals to control a first subsystem of a system, the first set of control signals generated in accordance with a time specification corresponding to the first subsystem and a time reference corresponding to the first subsystem; and

concurrently generating a second set of control signals to control a second subsystem of the communication device, the second set of control signals generated in accordance with a time specification corresponding to the second subsystem and a time reference corresponding to the second subsystem.

16. The method of claim 15 wherein generating a first set of control signals and concurrently generating a second set of control signals includes executing a first instruction thread and concurrently executing a second instruction thread, the first instruction thread containing the time specification corresponding to the first subsystem and the second instruction thread containing the time specification corresponding to the second subsystem.

17. The method of claim 16 wherein the time reference corresponding to the first subsystem is a combination of a common time reference and a timing offset determined for the first subsystem, and the time reference corresponding to the second subsystem is a combination of the common time reference and a timing offset determined for the second subsystem.

18. The method of claim 17 further comprising the antecedent operations of:

storing the first instruction thread and the second instruction thread to a memory device; and

storing an initial timing offset determined for the first subsystem to a first timing offset register, and storing an initial timing offset determined for the second subsystem to a second timing offset register.

19. The method of claim 18 wherein the operations of storing are performed by an external entity through an external data interface coupling the memory device, the first timing offset register and the second timing offset register to the microcontroller.

20. The method of claim 15 wherein the system is a communication device having a transmitter and a receiver.

21. The method of claim 17 further comprising:

adjusting the timing offset determined for the transmitter and adjusting the timing offset for the receiver using different values to effect a transmission timing advance.

22. A machine-readable medium having one or more executable instructions stored thereon, which, when executed by a digital processing system, causes the digital processing system to perform a method, the method comprising:

providing a plurality of instruction threads, each instruction thread containing a timing specification;

providing a plurality of distinct timing references, each timing reference corresponding to one of the plurality of instruction threads; and

concurrently executing each instruction thread in accordance with the corresponding timing reference such that the execution of each of the plurality of instruction threads generates control signals independently, at specified times, for a corresponding subsystem of a communication device.

23. The machine-readable medium of claim 22 wherein an external entity loads the plurality of instruction threads to a memory device via an external data interface, the external data interface coupled to the external entity and to the memory device.

24. The machine-readable medium of claim 22 wherein each time reference corresponding to an instruction thread is a combination of a common time reference with a timing offset specific to each instruction thread.

25. The machine-readable medium of claim 24 wherein each timing offset is stored in a separate timing offset register such that each timing offset can be independently modified by the external entity via the external device interface.

26. The machine-readable medium of claim 23 wherein the memory device comprises random access memory.

27. The machine-readable memory of claim 25 wherein a modification to a timing offset of an instruction thread is stored in a corresponding shadow timing offset register such that the timing offset of each timing offset register is buffered in the corresponding shadow timing offset register.

28. The machine-readable medium of claim 27 wherein each instruction thread contains a dedicated instruction such that execution of the dedicated instruction causes the timing offset of the corresponding timing offset register to be buffered in the corresponding shadow timing offset register.

29. The machine-readable medium of claim 28 wherein each of the plurality of instruction threads has a corresponding program counter to provide an address for each instruction of an instruction thread from the corresponding program counter.

30. The machine-readable medium of claim 29 wherein each program counter has a distinct reset value, each reset value indicating a memory location entry point to the corresponding instruction thread.

31. The machine-readable medium of claim 30 wherein each distinct memory location entry point contains a jump instruction to a specified memory location containing the instruction thread corresponding to the program counter.

32. The machine-readable medium of claim 22 wherein the communication device is a user terminal of a telecommunications system and the plurality of corresponding subsystems of the device include the user terminal receiver and the user terminal transmitter.

33. The machine-readable medium of claim 32 wherein the telecommunications system is a time division duplex telecommunications system.

34. The machine-readable medium of claim 33 wherein the timing offset of the instruction thread corresponding to the user terminal transmitter and the timing offset of the instruction thread corresponding to the user terminal receiver are adjusted by different values, thereby effecting a transmission timing advance.

35. A portion of a cellular radio communications network comprising:

a base station;

a plurality of user terminals communicating through the base station, each user terminal having a plurality of independently controlled subsystems, each of the subsystems controlled through control signals concurrently generated by execution of a corresponding instruction thread containing a timing specification, wherein each instruction thread has a corresponding timing reference.

36. The portion of a cellular communications network of claim 35 wherein the communication network is a time division duplex telecommunications network and the plurality of independently controlled subsystems includes a user terminal receiver and a user terminal transmitter.

37. The portion of a cellular communications network of claim 36 wherein each time reference corresponding to an instruction thread is obtained by combining a common time reference with a timing offset specific to each instruction thread.

38. The portion of a cellular communications network of claim 37 wherein each timing offset is stored in a separate timing offset register.

39. The portion of a cellular communications network of claim 36 further comprising:

an external data interface coupled to each separate timing offset register such that each timing offset can be adjusted independently by an external device.

40. The portion of a cellular communications network of claim 39 wherein the one or more memory devices comprise random access memory coupled to the external data interface such that the plurality of instruction threads, corresponding timing sequences and corresponding timing references can be loaded into the one or more memory devices.

41. The portion of a cellular communications network of claim 39 further comprising a plurality of shadow timing offset registers, each shadow timing offset register corresponding to a timing offset register such that the timing offset of each timing offset register is buffered in the corresponding shadow timing offset register.

42. The portion of a cellular communications network of claim 41 wherein each instruction thread contains a dedicated instruction such that execution of the dedicated instruction causes the timing offset of the corresponding timing offset register to be buffered in the corresponding shadow timing offset register.

43. The portion of a cellular communications network of claim 36 wherein each of the plurality of instruction threads has a corresponding program counter coupled to one of the one or more instruction execution units such that the one instruction execution unit obtains an address for each instruction of an instruction thread from the corresponding program counter.

44. The portion of a cellular communications network of claim 39 wherein each program counter has a distinct reset value, each reset value indicating a memory location entry point to the corresponding instruction thread.

45. The portion of a cellular communications network of claim 44 wherein each distinct memory location entry point contains a jump instruction to direct the one instruction execution unit to a specified memory location containing the instruction thread corresponding to the program counter.

46. The portion of a cellular communications network of claim 37 wherein the timing offset of the instruction thread corresponding to the user terminal transmitter and the timing offset of the instruction thread corresponding to the user terminal receiver are adjusted by different values, effecting a transmission timing advance thereby.