Super lattice modification of overlying transistor

• US 20040195562A1
• Filed: 11/25/2003
• Published: 10/07/2004
• Est. Priority Date: 11/25/2002
• Status: Active Grant

• Current Assignee: Infineon Technologies Americas Corp. (Infineon Technologies AG)
• Original Assignee: Clearfield, Inc
• Inventors: Munns, Gordon
• Granted Patent: US 7,112,830 B2
• Time in Patent Office: Days
• US Class Current: 257/1
• CPC Class Codes: H01L 29/155 Comprising only semiconductor materials H01L29/154 takes precedence
• CPC Class Codes: H01L 29/2003 Nitride compounds
• CPC Class Codes: H01L 29/66462 with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT
• CPC Class Codes: H01L 29/7787 with wide bandgap charge-carrier supplying layer, e.g. direct single heterostructure MODFET

Abstract

The invention provides a device having a substrate, a buffer region positioned upon the substrate, wherein the buffer region has an upper buffer region and a lower buffer region, a heterojunction region positioned upon the buffer region, and a superlattice positioned between the lower buffer region and the upper buffer region, wherein the device is configured to function as a heterojunction field effect transistor.

Claims

1. A device comprising:

a substrate;

a buffer region positioned upon said substrate, wherein said buffer region comprises an upper buffer region and a lower buffer region;

a heteroj unction region positioned upon said buffer region; and

a superlattice positioned between said lower buffer region and said upper buffer region, wherein said superlattice comprises individual layers of GaN and Al_xGa_1-xN,

wherein said device is configured to function as a heterojunction field effect transistor.

2. The device of claim 1, wherein x is from about 0.01 to about 0.40.

3. The device of claim 2, wherein x is from about 0.02 to about 0.30.

4. The device of claim 1, wherein said superlattice comprises from about 2 to about 500 individual layers.

5. The device of claim 4, wherein said superlattice comprises from about 5 to about 100 individual layers.

6. The device of claim 1, wherein said lower buffer region is about 0.1 to about 3 μ

m thick.

7. The device of claim 6, wherein said lower buffer region is about 0.2 to about 0.5 μ

m thick.

8. The device of claim 1, wherein said individual layers of said superlattice are from about 5 to about 200 Å

thick.

9. The device of claim 1, wherein said heterojunction region comprises a first layer and a second layer, wherein said second layer is positioned directly above said upper buffer region, and said first layer is positioned directly above said second layer.

10. The device of claim 9, wherein said first layer and said second layer both comprise Al_yGa_1-yN, where y has a value of from about 0.1 to 1.

11. The device of claim 10, wherein said first layer is doped and said second layer is undoped.

12. The device of claim 11, wherein said first layer has a thickness of from about 100 to 300 Å

, and said second layer has a thickness of from about 2 to 30 Å

.

13. The device of claim 1, wherein said heterojunction region comprises Al_bGa_1-bN, where b has a value of from about 0.1 to 1.

14. The device of claim 13, wherein said Al_bGa_1-bN is pulse doped.

15. The device of claim 14, wherein said pulse doped Al_bGa_1-bN has a trilayer structure with a layer of dopant with a thickness of about 2 to 10 Å

between two layers of undoped Al_bGa_1-bN.

16. The device of claim 1, wherein said substrate comprises silicon.

17. A device comprising:

a substrate comprising sapphire;

a buffer region positioned upon said substrate, wherein said buffer region comprises an upper buffer region and a lower buffer region;

a heterojunction region positioned upon said buffer region; and

a superlattice positioned between said lower buffer region and said upper buffer region, wherein said superlattice comprises individual layers of GaN and Al_xGa_1-xN.,

wherein said device is configured to function as a heterojunction field effect transistor.

18. The device of claim 17, wherein x is about 0.28

19. The device of claim 17, wherein said superlattice comprises from about 4 to about 50 individual layers.

20. The device of claim 19, wherein said superlattice comprises about 10 individual layers.

21. The device of claim 17, wherein said lower buffer region comprises at least one layer of AlN, and at least one layer of GaN.

22. The device of claim 21, wherein said at least one layer of GaN is about 0.4 thick, and said at least one layer of AlN is about 300 Å

thick.

23. The device of claim 17, wherein said GaN layers of said superlattice are about 80Å

thick, and said Al_xGa_1-xN layers are about 100 Å

thick.

24. A device comprising:

a substrate comprising silicon carbide;

a buffer region positioned upon said substrate, wherein said buffer region comprises an upper buffer region and a lower buffer region;

a heterojunction region positioned upon said buffer region; and

a superlattice positioned between said lower buffer region and said upper buffer region, wherein said superlattice comprises individual layers of GaN and Al_xGa_1-xN.,

wherein said device is configured to function as a heterojunction field effect transistor.

25. The device of claim 24, wherein x is about 0.02

26. The device of claim 24, wherein said superlattice comprises from about 4 to about 50 individual layers.

27. The device of claim 26, wherein said superlattice comprises about 10 individual layers.

28. The device of claim 24, wherein said lower buffer region comprises at least one layer of AlN, and at least one layer of GaN.

29. The device of claim 28, wherein said at least one layer of GaN is about 0.4 thick, and said at least one layer of AlN is about 1000 Å

thick.

30. The device of claim 24, wherein said GaN layers of said superlattice are about 80Å

thick, and said Al_xGa_1-xN layers are about 100 Å

thick.