Vertical type power MOSFET having trenched gate structure

• US 20040195619A1
• Filed: 04/19/2004
• Published: 10/07/2004
• Est. Priority Date: 06/29/2001
• Status: Active Grant

• Current Assignee: Syotaro Ono, Yusuke Kawaguchi
• Original Assignee: Syotaro Ono, Yusuke Kawaguchi
• Inventors: Kawaguchi, Yusuke, Ono, Syotaro
• Granted Patent: US 7,045,426 B2
• Time in Patent Office: Days
• US Class Current: 257/330
• CPC Class Codes: H01L 29/0847 of field-effect transistors with insulated gate H01L29/0653 takes precedence; with a passive supplementary region between source or drain and substrate related to punch-through, capacity or isolation phenomena H01L29/1079; with LDD or DDD structure H01L29/7833; for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/0878 Impurity concentration or distribution
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 29/7828 without inversion channel, e.g. vertical ACCUFETs, normally-on vertical MISFETs

Abstract

A power MOSFET comprising a drain layer of a first conductivity type, a drift layer of the first conductivity type provided on the drain layer, a base layer of a first or a second conductivity type provided on the drift layer, a source region of the first conductivity type provided on the base layer, a gate insulating film formed on an inner wall surface of a trench penetrating the base layer and reaching at the drift layer, and a gate electrode provided on the gate insulating film inside the trench, wherein the gate insulating film is formed such that a portion thereof adjacent to the drift layer is thicker than a portion thereof adjacent to the base layer, and the drift layer has an impurity concentration gradient higher in the vicinity of the drain layer and lower in the vicinity of the source region along a depth direction of trench.

Claims

1-30. -30. Canceled.

31. A method of manufacturing a power MOSFET, comprising:

epitaxially growing a drift layer of a first conductivity type on a first conductivity type semiconductor substrate used as a drain layer, said drift layer being doped with impurities having a concentration distribution increasing up to said semiconductor substrate;

epitaxially growing a base layer of a second conductivity type on said drift layer;

forming a source region of the first conductivity type on said base layer;

forming a trench penetrating said source region and said base layer to reach at said drift layer; and

forming a trenched gate structure including a gate insulating film and a gate electrode, said gate insulating film having a thin portion facing said base layer and a thick portion facing said drift layer.

32. The method of manufacturing a power MOSFET according to claim 31, wherein said forming the drift layer comprises:

forming a first epitaxial layer of the first conductivity type on said semiconductor substrate with a first impurity concentration;

forming a second epitaxial layer of the first conductivity type on said first epitaxial layer with a second impurity concentration lower than the first impurity concentration of said first epitaxial layer; and

heat treating said first and second epitaxial layers for smoothing the first and second impurity concentrations.

33. The method of manufacturing a power MOSFET according to claim 32, which further comprises:

implanting impurities from a surface of said second epitaxial layer up to a predetermined depth thereof; and

diffusing the implanted impurities into said second epitaxial layer to form a peak of the impurity concentration in said second epitaxial layer.