Termination structure of DMOS device
First Claim
1. A trenched DMOS device having a termination structure, the trenched DMOS device comprising:
- a silicon substrate of a first conductive type, having a first epitaxial layer of the first conductive type and a second epitaxial layer of a second conductive type formed thereon;
a DMOS trench, formed in the first epitaxial layer and the second epitaxial layer;
a first trench, formed in the first epitaxial layer and the second epitaxial layer disposed close to an edge of the second epitaxial layer, the first trench to be utilized as a main portion of the termination structure having a bottom disposed in the first epitaxial layer;
a second trench disposed between the DMOS trench and the first trench, the second trench having another bottom disposed in the second epitaxial layer adjacent to a region of the second conductive type;
a gate oxide layer on the DMOS trench and the first trench, the gate oxide layer having extended portions covering an upper surface of the second epitaxial layer adjacent the DMOS trench and of the second epitaxial layer adjacent the first trench;
a first polysilicon layer, formed in the DMOS trench;
a second polysilicon layer, formed over the gate oxide layer in the first trench, having another extended portion covering the upper surface of the second epitaxial layer adjacent the first trench, the second polysilicon layer having an opening to expose the gate oxide layer disposed at the bottom of the first trench to split the second polysilicon layer into two discrete parts;
an isolation layer, formed on the first polysilicon layer in the DMOS trench and extended portions of the gate oxide layer adjacent the DMOS trench, on the second polysilicon layer, and on the gate oxide layer over the second epitaxial layer at the bottom of the first trench, the isolation layer having a first contact window to expose the second polysilicon layer over the second epitaxial layer and a second contact window to expose the second trench; and
a source metal contact layer, formed over the isolation layer and filling both the first contact window and the second contact window, having a connection with a source of the DMOS device and further having an edge beside the first contact window.
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Accused Products
Abstract
In one embodiment of the invention, a semiconductor device set comprises at least one trench-typed MOSFET and a trench-typed termination structure. The trench-typed MOSFET has a trench profile and comprises a gate oxide layer in the trench profile, and a polysilicon layer on the gate oxide layer. The trench-typed termination structure has a trench profile and comprises an oxide layer in the trench profile. A termination polysilicon layer with discrete features separates the termination polysilicon layer. An isolation layer covers the termination polysilicon layer and filling the discrete features. The trench-typed MOSFET and the trench-typed termination structure may be formed on a DMOS device comprising an N+ silicon substrate, an N epitaxial layer on the N+ silicon substrate, and a P epitaxial layer on the N epitaxial layer. The trench profiles of the trench-typed MOSFET and of the trench-typed termination structure may penetrate through the P epitaxial layer into the N epitaxial layer.
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Citations
25 Claims
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1. A trenched DMOS device having a termination structure, the trenched DMOS device comprising:
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a silicon substrate of a first conductive type, having a first epitaxial layer of the first conductive type and a second epitaxial layer of a second conductive type formed thereon;
a DMOS trench, formed in the first epitaxial layer and the second epitaxial layer;
a first trench, formed in the first epitaxial layer and the second epitaxial layer disposed close to an edge of the second epitaxial layer, the first trench to be utilized as a main portion of the termination structure having a bottom disposed in the first epitaxial layer;
a second trench disposed between the DMOS trench and the first trench, the second trench having another bottom disposed in the second epitaxial layer adjacent to a region of the second conductive type;
a gate oxide layer on the DMOS trench and the first trench, the gate oxide layer having extended portions covering an upper surface of the second epitaxial layer adjacent the DMOS trench and of the second epitaxial layer adjacent the first trench;
a first polysilicon layer, formed in the DMOS trench;
a second polysilicon layer, formed over the gate oxide layer in the first trench, having another extended portion covering the upper surface of the second epitaxial layer adjacent the first trench, the second polysilicon layer having an opening to expose the gate oxide layer disposed at the bottom of the first trench to split the second polysilicon layer into two discrete parts;
an isolation layer, formed on the first polysilicon layer in the DMOS trench and extended portions of the gate oxide layer adjacent the DMOS trench, on the second polysilicon layer, and on the gate oxide layer over the second epitaxial layer at the bottom of the first trench, the isolation layer having a first contact window to expose the second polysilicon layer over the second epitaxial layer and a second contact window to expose the second trench; and
a source metal contact layer, formed over the isolation layer and filling both the first contact window and the second contact window, having a connection with a source of the DMOS device and further having an edge beside the first contact window. - View Dependent Claims (2, 3, 4, 5, 6, 7, 20)
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8. A trenched DMOS device having a termination structure, the trenched DMOS device comprising:
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a silicon substrate of a first conductive type, having a first epitaxial layer of the first conductive type and a second epitaxial layer of a second conductive type formed thereon;
a pair of DMOS gates, formed in the first epitaxial layer and the second epitaxial layer and being spaced by a body contact window;
a first trench, formed in the first epitaxial layer and the second epitaxial layer disposed close to an edge of the second epitaxial layer, the first trench to be utilized as a main portion of the termination structure having a bottom disposed in the first epitaxial layer;
a second trench disposed between the DMOS gates and the first trench, the second trench having a bottom disposed in the second epitaxial layer adjacent to a region of the second conductive type;
a gate oxide layer on the first trench, the gate oxide layer having extended portions covering an upper surface of the second epitaxial layer adjacent the first trench;
a second polysilicon layer, formed over the gate oxide layer in the first trench, having another extended portion covering the upper surface of the second epitaxial layer adjacent the first trench, the second polysilicon layer having an opening to expose the gate oxide layer disposed at the bottom of the first trench to split the second polysilicon layer into two discrete parts;
an isolation layer, formed on the DMOS gate, on the second polysilicon layer, and on the gate oxide layer over the second epitaxial layer at the bottom of the first trench, the isolation layer having a first contact window to expose the second polysilicon layer over the second epitaxial layer and a second contact window to expose the second trench; and
a source metal contact layer, formed over the isolation layer and filling both the first contact window and the second contact window, having a connection with a source of the DMOS device and further having an edge beside the first contact window. - View Dependent Claims (9, 10)
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11. A fabrication method of forming a DMOS device and a termination thereof comprising:
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forming a first epitaxial layer of a first conductive type over a silicon substrate of the first conductive type;
forming a second epitaxial layer of a second conductive type over the first epitaxial layer;
patterning and etching the first and second epitaxial layers to form a plurality of DMOS trenches and a first trench, the DMOS trenches and the first trench having bottoms disposed in the first epitaxial layer;
forming a gate oxide layer over the exposed surface by thermal oxidation;
forming a polysilicon layer over all the exposed surfaces to fill the DMOS trenches;
patterning and etching the polysilicon layer to form a plurality of gate electrodes and a termination polysilicon layer, and the termination polysilicon layer having an opening to expose a bottom surface of the first trench and an extended portion covering the second epitaxial layer adjacent to the first trench;
forming a photoresist pattern to define source regions and forming the source regions of the first conductivity type;
forming an isolation layer over the exposed surfaces;
patterning and etching the isolation layer to form a plurality of body contact windows over the source regions, a second contact window over the second epitaxial layer between the first trench and the DMOS trench, and a first contact window over the extended portion of the termination polysilicon layer;
implanting dopants of a second conductive type through the body contact windows and the second contact window;
forming a source metal contact layer over the exposed surface to fill the body contact windows, first contact window, and the second contact window; and
patterning and etching to remove the source metal contact layer over the termination structure. - View Dependent Claims (12, 13, 14, 15, 16, 17, 18, 19, 21)
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22. A semiconductor device set comprising at least one trench-typed MOSFET and a trench-typed termination structure;
- wherein the trench-typed MOSFET has a trench profile and comprises a gate oxide layer in the trench profile, and a polysilicon layer on the gate oxide layer;
wherein the trench-typed termination structure has a trench profile and comprises an oxide layer in the trench profile, a termination polysilicon layer with discrete features separating the termination polysilicon layer, an isolation layer covering the termination polysilicon layer and filling the discrete features. - View Dependent Claims (23, 24, 25)
- wherein the trench-typed MOSFET has a trench profile and comprises a gate oxide layer in the trench profile, and a polysilicon layer on the gate oxide layer;
Specification