High-Q inductor device with a shielding pattern embedded in a substrate

• US 20040195650A1
• Filed: 04/04/2003
• Published: 10/07/2004
• Est. Priority Date: 04/04/2003
• Status: Abandoned Application

• Current Assignee: Silicon Integrated Systems Corporation (Silicon Integrated Systems Corporation Taiwan)
• Original Assignee: Silicon Integrated Systems Corporation (Silicon Integrated Systems Corporation Taiwan)
• Inventors: Huang, Kuo-Chung, Yang, Tsung-Ju, Hsu, Chang-Feng, Huang, Wei-Fu, Chen, Hsiang-Tsu
• Application Number:
  US10/406,939
• Publication Number:
  US 20040195650A1
• Time in Patent Office: Days
• US Class Current: 257/531
• CPC Class Codes: H01L 27/08 including only semiconductor components of a single kind
• CPC Class Codes: H01L 28/10 Inductors

Abstract

An insulating layer is formed over a surface of a semiconductor substrate. A conductive film is formed over the insulating layer and separated from the semiconductor substrate. A shielding pattern is embedded within the semiconductor substrate and includes a plurality of isolation portions and a plurality of highly doped portions. The isolation portions are distributed within the semiconductor substrate for dividing the surface of the semiconductor into a plurality of regions unconnected with each other. The highly doped portions are formed within the semiconductor substrate and close to the surface, electrically insulated from each other by the isolation portions. The shielding pattern may further include a plurality of silicide layers formed on the highly doped portions and an ion implanted well for accommodating the isolation portions and the highly doped portions.

Claims

1. A high-Q inductor device, comprising:

a semiconductor substrate having a surface;

an insulating layer formed over the surface of the semiconductor substrate;

a conductive film formed over the insulating layer and separated from the semiconductor substrate, the conductive film having two terminals and serving as a current path; and

a shielding pattern embedded in the semiconductor substrate, including;

a plurality of isolation portions distributed in the semiconductor substrate, each of which has a bottom intruding the semiconductor substrate and a top appearing from the surface of the semiconductor substrate, thereby dividing the surface into a plurality of regions unconnected with each other, and

a plurality of highly doped portions formed in the semiconductor substrate and close to the surface, each of which is electrically insulated from each other through the plurality of isolation portions.

2. The high-Q inductor device according to claim 1, wherein the semiconductor substrate is made of silicon.

3. The high-Q inductor device according to claim 1, wherein the semiconductor substrate has a P-type conductivity and each of the plurality of the highly doped portions has an N-type conductivity.

4. The high-Q inductor device according to claim 1, wherein the semiconductor substrate has an N-type conductivity and each of the plurality of the highly doped portions has a P-type conductivity.

5. The high-Q inductor device according to claim 1, wherein each of the plurality of the isolation portions is formed of a shallow trench isolation.

6. The high-Q inductor device according to claim 1, wherein the plurality of the isolation portions are arranged in form of a radiative matrix.

7. The high-Q inductor device according to claim 1, wherein the plurality of the isolation portions are arranged as perpendicular to each other.

8. The high-Q inductor device according to claim 1, wherein the conductive film is formed in shape of a spiral belt.

9. The high-Q inductor device according to claim 1, further comprising:

a passivation layer for covering the conductive film.

10. The high-Q inductor device according to claim 1, wherein the shielding pattern further comprises:

a plurality of silicide layers formed on the plurality of the highly doped portions and electrically insulated from each other by the plurality of isolation portions.

11. The high-Q inductor device according to claim 10, wherein each of the plurality of silicide layers is formed of a salicide layer.

12. The high-Q inductor device according to claim 1, wherein the shielding pattern further comprises:

an ion implanted well formed in the semiconductor substrate for accommodating the plurality of isolation portions and the plurality of highly doped portions.

13. The high-Q inductor device according to claim 12, wherein the semiconductor substrate has a P-type conductivity, the ion implanted well has an N-type conductivity, and each of the plurality of the highly doped portions has an N-type conductivity.

14. The high-Q inductor device according to claim 12, wherein the semiconductor substrate has a P-type conductivity, the ion implanted well has an N-type conductivity, and each of the plurality of the highly doped portions has a P-type conductivity.

15. The high-Q inductor device according to claim 12, wherein the semiconductor substrate has an N-type conductivity, the ion implanted well has a P-type conductivity, and each of the plurality of the highly doped portions has a P-type conductivity.

16. The high-Q inductor device according to claim 12, wherein the semiconductor substrate has an N-type conductivity, the ion implanted well has a P-type conductivity, and each of the plurality of the highly doped portions has an N-type conductivity.