Electronic package and method

• US 20040195701A1
• Filed: 01/06/2004
• Published: 10/07/2004
• Est. Priority Date: 01/07/2003
• Status: Active Grant

• Current Assignee: ISMAT Corporation
• Original Assignee: Abbas Ismail Attarwala
• Inventors: Attarwala, Abbas Ismail
• Granted Patent: US 7,105,931 B2
• Time in Patent Office: Days
• US Class Current: 257/783
• CPC Class Codes: H01L 21/4846 Leads on or in insulating or insulated substrates, e.g. metallisation H01L21/4821 takes precedence; metallisation of ceramics in general C04B41/51; printed circuits H05K3/00
• CPC Class Codes: H01L 21/50 Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
• CPC Class Codes: H01L 21/563 Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/13099 Material
• CPC Class Codes: H01L 2224/13111 Tin [Sn] as principal constituent
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/29111 Tin [Sn] as principal constituent
• CPC Class Codes: H01L 2224/2919 with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/32245 the item being metallic
• CPC Class Codes: H01L 2224/45015 being circular
• CPC Class Codes: H01L 2224/45144 Gold (Au) as principal constituent
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/49109 outside the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/49171 Fan-out arrangements
• CPC Class Codes: H01L 2224/73203 Bump and layer connectors
• CPC Class Codes: H01L 2224/73204 the bump connector being embedded into the layer connector
• CPC Class Codes: H01L 2224/73253 Bump and layer connectors
• CPC Class Codes: H01L 2224/73265 : Layer and wire connectors
• CPC Class Codes: H01L 2224/75265 : in the lower part of the bonding apparatus, e.g. in the apparatus chuck
• CPC Class Codes: H01L 2224/81 : using a bump connector
• CPC Class Codes: H01L 2224/81222 : Induction heating, i.e. eddy currents
• CPC Class Codes: H01L 2224/81805 : involving forming a eutectic alloy at the bonding interface
• CPC Class Codes: H01L 2224/83102 : using surface energy, e.g. capillary forces
• CPC Class Codes: H01L 2224/83855 : Hardening the adhesive by curing, i.e. thermosetting
• CPC Class Codes: H01L 2224/85 : using a wire connector
• CPC Class Codes: H01L 2224/92125 : the second connecting process involving a layer connector
• CPC Class Codes: H01L 2224/97 : the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 23/145 : Organic substrates, e.g. plastic
• CPC Class Codes: H01L 23/36 : Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks H01L23/28, H01L23/40, H01L23/42, H01L23/44, H01L23/46 take precedence; heating H01L23/345
• CPC Class Codes: H01L 23/49816 : Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
• CPC Class Codes: H01L 24/13 : of an individual bump connector
• CPC Class Codes: H01L 24/16 : of an individual bump connector
• CPC Class Codes: H01L 24/29 : of an individual layer connector
• CPC Class Codes: H01L 24/31 : Structure, shape, material or disposition of the layer connectors after the connecting process
• CPC Class Codes: H01L 24/45 : of an individual wire connector
• CPC Class Codes: H01L 24/48 : of an individual wire connector
• CPC Class Codes: H01L 24/49 : of a plurality of wire connectors
• CPC Class Codes: H01L 24/50 : Tape automated bonding [TAB] connectors, i.e. film carriers; Manufacturing methods related thereto thin flexible metallic tape with or without a film carrier H01L23/49572, flexible insulating substrates H01L23/4985, H01L23/5387
• CPC Class Codes: H01L 24/73 : Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
• CPC Class Codes: H01L 24/75 : Apparatus for connecting with bump connectors or layer connectors
• CPC Class Codes: H01L 24/81 : using a bump connector
• CPC Class Codes: H01L 24/86 : using tape automated bonding [TAB]
• CPC Class Codes: H01L 24/97 : the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00011 : Not relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01005 : Boron [B]
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01014 : Silicon [Si]
• CPC Class Codes: H01L 2924/01027 : Cobalt [Co]
• CPC Class Codes: H01L 2924/01028 : Nickel [Ni]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01039 : Yttrium [Y]
• CPC Class Codes: H01L 2924/01047 : Silver [Ag]
• CPC Class Codes: H01L 2924/0105 : Tin [Sn]
• CPC Class Codes: H01L 2924/01076 : Osmium [Os]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/0132 : Binary Alloys
• CPC Class Codes: H01L 2924/01322 : Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
• CPC Class Codes: H01L 2924/01327 : Intermediate phases, i.e. intermetallics compounds
• CPC Class Codes: H01L 2924/0133 : Ternary Alloys
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/0665 : Epoxy resin
• CPC Class Codes: H01L 2924/078 : Adhesive characteristics other than chemical
• CPC Class Codes: H01L 2924/10253 : Silicon [Si]
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/15153 : the die mounting substrate comprising a recess for hosting the device
• CPC Class Codes: H01L 2924/1517 : Multilayer substrate
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/1532 : the connection portion being formed on the die mounting surface of the substrate
• CPC Class Codes: H01L 2924/15724 : Aluminium [Al] as principal constituent
• CPC Class Codes: H01L 2924/15747 : Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2924/15787 : Ceramics, e.g. crystalline carbides, nitrides or oxides
• CPC Class Codes: H01L 2924/16195 : Flat cap [not enclosing an internal cavity]
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/3025 : Electromagnetic shielding
• CPC Class Codes: H01L 2924/3512 : Cracking

Abstract

An electronic package substrate for an electronic package that includes an adhesive bonding member having two planar surfaces and an orifice there through for receiving a chip and a circuitized member having two planar surfaces, one surface being bonded to one of the planar surfaces of the bonding member, said circuitized member being electrically connectable to the chip. An electronic package for a wire bonded chip or tab bonded chip that includes an adhesive bonding member having two planar surfaces and an orifice there through; a circuitized member bonded to one of the planar surfaces and having an orifice there through overlying the orifice in the bonding member; a support member bonded to the other planar surface, blocking the orifices, thereby forming a cavity; and a chip bonded within the cavity to the support member and electrically connected to the circuitized member. An electronic package substrate for an electronic package for a flip chip includes an adhesive bonding member having two planar surfaces and an orifice there through, a circuitized member bonded to one of the planar surfaces and blocking the orifice, thereby forming a cavity for receiving a flip chip, and an array of solder pads on the circuitized member within the cavity. A process for fabricating an electronic package substrate including the steps of fabricating an adhesive bonding member and a circuitized member, aligning the members with respect to each other, sandwiching the members together, and bonding the members together with heat and pressure.

Claims

1. An electronic package substrate for an electronic package, comprising:

an adhesive bonding member having two planar surfaces and an orifice there through for receiving a chip; and

a circuitized member having two planar surfaces, one surface being bonded to one of the planar surfaces of the bonding member, said circuitized member being electrically connectable to the chip.

2. The electronic package substrate of claim 1 further including a solder terminal electrically connected to a planar surface of the circuitized member.

3. The electronic package substrate of claim 1 wherein the bonding member is a structural support for the substrate.

4. The electronic package substrate of claim 1 wherein the bonding member is fabricated from a glass-fiber-reinforced/filled epoxy resin.

5. The electronic package substrate of claim 4 wherein the bonding member is fabricated from FR-4.

6. The electronic package substrate of claim 4 wherein the bonding member is fabricated from BT resin.

7. The electronic package substrate of claim 1 wherein the circuitized member is a polyimide substrate with photo lithographically developed electrically conductive traces.

8. The electronic package substrate of claim 1 wherein the bonding member is electrically conductive.

9. The electronic package substrate of claim 8 wherein the bonding member is fabricated with silver particles therein.

10. The electronic package substrate of claim 1 wherein the bonding member is electrically nonconductive.

11. The electronic package substrate of claim 1 further including a support member bonded to a planar surface of the bonding member.

12. An electronic package substrate for an electronic package, comprising:

an adhesive bonding member having two planar surfaces and an orifice there through;

a circuitized member bonded to one of the planar surfaces and having an orifice there through overlying the orifice in the bonding member; and

a support member bonded to the other planar surface, blocking the orifices, and thereby forming a cavity in the substrate for receiving a chip.

13. The electronic package substrate of claim 12 wherein the support member is thermally conductive.

14. The electronic package substrate of claim 12 wherein the support member is a metal slug cut from sheet stock.

15. The metal slug of claim 14 wherein the slug has exterior facing ridges on one surface.

16. The electronic package substrate of claim 12 wherein the support member is electrically conductive.

17. An electronic package substrate for an electronic package, comprising:

an adhesive bonding member having two planar surfaces and an orifice there through, prior to bonding said bonding member being solid and substantially rigid;

a circuitized member bonded to one of the planar surfaces and having an orifice there through overlying the orifice in the bonding member; and

a support member bonded to the other planar surface, blocking the orifices, and thereby forming a cavity in the substrate for receiving a chip.

18. The electronic package substrate of claim 17 wherein the adhesive bonding member is fabricated from a solid, planar sheet of adhesive.

19. An array of electronic package substrates, comprising:

adhesive bonding members each having two planar surfaces and an orifice there through;

circuitized members each bonded to one of the planar surfaces and having an orifice there through each overlying the orifices in the bonding members;

support members each bonded to the other planar surface, blocking the orifices, and thereby forming cavities in the substrates for receiving a chip; and

a frame surrounding and connecting the bonding members.

20. An electronic package, comprising:

an adhesive bonding member having two planar surfaces and an orifice there through;

a circuitized member bonded to one of the planar surfaces and having an orifice there through overlying the orifice in the bonding member;

a support member bonded to the other planar surface, blocking the orifices and forming a cavity; and

a chip bonded within the cavity to the support member.

21. The electronic package of claim 20 wherein the adhesive bonding member is fabricated from a glass-fiber-reinforced/filled epoxy resin.

22. The electronic package of claim 20 wherein the chip within the cavity is electrically connected to the circuitized member.

23. An electronic package substrate for an electronic package, comprising:

an adhesive bonding member having two planar surfaces and an orifice there through;

a circuitized member bonded to one of the planar surfaces and having an orifice there through overlying the orifice in the bonding member;

an electrically conductive, support member bonded to the other planar surface, blocking the orifices and forming a cavity for receiving a chip; and

an electrical conductor electrically connecting the support member such that when the support member and the conductor are grounded, a chip within the cavity is shielded from exterior fields.

24. The electronic package substrate of claim 23 wherein the support member forms a ground plane.

25. The electronic package substrate of claim 23 wherein the support member and the adhesive bonding member are both thermally and electrically conductive.

26. The electronic package substrate of claim 23 wherein the bonding member contains dispersed, electrically conductive elements.

27. The electronic package substrate of claim 23 wherein a chip contains a circuit that is groundable to the electrical conductor.

28. An electronic package substrate for an electronic package, comprising:

an adhesive bonding member having two planar surfaces and an orifice there through, said bonding member having an upper and a lower electrically conductive cladding connected by an electrically conducting via and said bonding member otherwise being electrically non-conductive;

a circuitized member bonded to one of the planar surfaces and having an orifice there through overlying the orifice in the bonding member;

an electrically conductive, support member bonded to the other planar surface, blocking the orifices and forming a cavity for receiving a chip; and

an electrical conductor electrically connecting the support member such that when the support member and the conductor are grounded, a chip within the cavity is shielded from exterior fields.

29. The electronic package substrate of claim 28 wherein the upper and lower cladding on the bonding member is copper.

30. An electronic package substrate for an electronic package, comprising:

an adhesive bonding member having two planar surfaces and an orifice there through, said bonding member having an upper and a lower electrically conductive cladding connected by an electrically conducting via;

a circuitized member bonded to one of the planar surfaces and having an orifice there through overlying the orifice in the bonding member, said circuitized member being dimensioned to form a ledge on the upper cladding of the bonding member, said upper cladding having a metallized layer to which wire bonds from a chip may be attached for grounding a circuit within the chip;

an electrically conductive, support member bonded to the other planar surface, blocking the orifices and forming a cavity for receiving a chip; and

an electrical conductor electrically connecting the support member such that when the member and the conductor are grounded, a chip within the cavity is shielded from exterior fields.

31. An electronic package substrate for an electronic package for a flip chip, comprising:

an adhesive bonding member having two planar surfaces and an orifice there through;

a circuitized member bonded to one of the planar surfaces and blocking the orifice, thereby forming a cavity for receiving a flip chip; and

an array of solder pads on the circuitized member within the cavity.

32. The substrate of claim 31 further including a stiffening member bonded to the bonding member and having an orifice there through overlying the orifice in the bonding member.

33. An electronic package for a flip chip, comprising:

an adhesive bonding member having two planar surfaces and an orifice there through;

a circuitized member bonded to one of the planar surfaces and blocking the orifice, thereby forming a cavity;

an array of solder pads on the circuitized member within the cavity; and

a flip chip mounted within the cavity and electrically connected to the solder pads.

34. The package of claim 33 further including an array of solder bumps on the flip chip in alignment with the array of solder pads, said bumps having a melting temperature above about 215°

C.

35. The package of claim 33 further including an array of solder bumps on the flip chip and array of solder balls on the circuitized member, said balls melt at least about 20°

C. lower than the bumps.

36. The package of claim 33 further including an induction heating concentrator operatively connected to the package by a magnetic field.

37. The package of claim 33 further including a stiffening member bonded to the bonding member and having an orifice there through overlying the orifice in the bonding member.

38. The package of claim 37 wherein the stiffening member is electrically nonconductive.

39. The package of claim 37 wherein the stiffening member is electrically conductive.

40. The package of claim 33 further including a heat sink and a second bonding member, the second bonding member being thermally conductive and bonding the heat sink to the flip chip.

41. The package of claim 33 further including a heat sink and a thermally conductive, cured adhesive paste bonding the heat sink to the flip chip.

42. The package of claim 33 further including an electrical ground plane formed by an electrically conductive heat sink and by an electrically conductive bonding member, both connectable to ground.

43. The package of claim 33 further including a shield against electromagnetic interference formed by an electrically conductive bonding member, an electrically conductive second bonding member, and an electrically conductive heat sink, all electrically connectable to ground.

44. A flip chip package substrate strip of electronic package substrates, comprising:

an array of electronic package substrates, each substrate having an adhesive bonding member having two planar surfaces and an orifice there through;

a circuitized member bonded to one of the planar surfaces and blocking the orifice, thereby forming a cavity for receiving a flip chip; and

an array of solder pads on the circuitized member within the cavity; and

a substrate frame surrounding each electronic package substrate, said frame is a support for the flip chip package substrate strip.

45. The flip chip package substrate strip of claim 44 further including an array of slots surrounding each substrate facilitating singulation.

46. The flip chip package substrate strip of claim 44 wherein the substrate frame is fabricated from the same material as the adhesive bonding member.

47. The flip chip package substrate strip of claim 44 further including a stiffening member bonded to the adhesive member and supporting the flip chip package substrate strip.

48. A process for fabricating an electronic package substrate, comprising:

fabricating an adhesive bonding member and a circuitized member;

aligning the members with respect to each other;

sandwiching the members together; and

bonding the members together with heat and pressure.

49. The process of claim 48 including forming simultaneously a plurality of substrates in an array surrounded by a frame formed by the bonding members.

50. A process for fabricating an electronic package substrate, comprising:

fabricating a thermally conductive support member, an adhesive bonding member, and a circuitized member;

sandwiching the members together; and

bonding adhesively the members together with heat and pressure.

51. The process of claim 50 wherein fabricating the support member includes cutting the member from metal sheet stock.

52. A process for fabricating an electronic package, comprising:

fabricating a thermally conductive support member, an adhesive bonding member, and a circuitized member;

sandwiching the members together, forming a cavity therein;

bonding adhesively the members together with heat and pressure;

bonding adhesively a chip to the support member within the cavity; and

connecting electrically the chip to the circuitized member.

53. A process for fabricating an electronic flip chip package, comprising:

fabricating an adhesive bonding member, a flip chip, and a circuitized member;

aligning the members with respect to each other;

sandwiching the members together;

bonding the members together with heat and pressure; and

connecting electrically the flip chip to the circuitized member.

54. The process of claim 53 wherein connecting electrically includes melting and bonding an array of solder bumps on the flip chip to the circuitized member.

55. The process of claim 54 wherein the melting of the solder bumps is melting by magnetic induction.

56. The process of claim 54 further including thereafter melting and bonding an array of solder balls to the circuitized member at a temperature of at least about 20°

C. lower than the temperature at which the bumps were melted.

57. The process of claim 56 wherein the melting of the solder balls is melting by magnetic induction.

58. The process of claim 53 further including bonding a heat sink to the flip chip after the chip has been connected to the circuitized member.