Operational amplifier with increased common mode input range

• US 20040196100A1
• Filed: 04/14/2004
• Published: 10/07/2004
• Est. Priority Date: 03/01/2002
• Status: Active Grant

• Current Assignee: Qualcomm, Inc.
• Original Assignee: Broadcom Corporation (Broadcom, Inc.)
• Inventors: Ranganathan, Sumant, Blecker, Eric B.
• Granted Patent: US 7,142,056 B2
• Time in Patent Office: Days
• US Class Current: 330/253
• CPC Class Codes: H03F 2203/45366 the AAC comprising multiple transistors parallel coupled at their gates only, e.g. in a cascode dif amp, only those forming the composite common source transistor
• CPC Class Codes: H03F 3/45183 Long tailed pairs H03F3/4521, H03F3/45237 take precedence
• CPC Class Codes: H03F 3/4565 Controlling the common source circuit of the differential amplifier

Abstract

An operational amplifier includes a first stage with a first differential transistor pair inputting a differential input signal at their gates, a first tail current source transistor connected to sources of the first differential transistor pair, and a load transistor pair connected in series with the drain of first differential transistor pair. An input stage includes a second differential transistor pair connected to respective drains of the first differential transistor pair at their gates, and a second tail current transistor connected to sources of the differential transistor pair. An output stage outputs a signal corresponding to the differential input signal.

Claims

10. An operational amplifier comprising:

a first stage inputting a differential input signal;

an input stage including a first differential transistor pair connected the first stage, and a first tail current source transistor connected to sources of the differential transistor pair; and

an output stage,

wherein the first stage includes;

a second differential transistor pair;

a second tail current source transistor connected to sources of the second differential transistor pair; and

a load transistor pair connected in series with drains of the second differential transistor pair, and

wherein substrates of the load transistor pair are connected to their respective sources, and

wherein the output stage is connected to the second differential transistor pair.

1. An operational amplifier comprising:

a first differential transistor pair receiving a differential input signal at their gates and having substrates connected to their respective sources,

a first tail current source transistor connected to sources of the first differential transistor pair, and

a load transistor pair connected in series with drains of the first differential transistor pair;

a second differential transistor pair having gates connected to respective drains of the first differential transistor pair at their gates, and a second tail current transistor connected to sources of the second differential transistor pair; and

an output stage connected to the second differential transistor pair.

2. The operational amplifier of claim 1, wherein transistors of the first differential pair are of the same polarity.

3. The operational amplifier of claim 1, wherein transistors of the load transistor pair are of the same polarity.

4. The operational amplifier of claim 1, wherein transistors of the first differential pair and transistors of the load transistor pair are all of the same polarity.

5. The operational amplifier of claim 1, wherein small signal model transconductance of transistors of the first differential pair and small signal model transconductance of transistors of the load transistor pair are substantially fixed relative to each other.

6. The operational amplifier of claim 1, wherein transistors of the first differential pair are PMOS transistors.

7. The operational amplifier of claim 1, wherein transistors of the load transistor pair are PMOS transistors.

8. The operational amplifier of claim 1, further including a current source connected to a gate of the first tail current source transistor that permits a squeezing of the first tail current source transistor.

9. The operational amplifier of claim 8, wherein the current source includes a third differential transistor pair whose gates are driven by the differential input signal.

11. The operational amplifier of claim 10, wherein transistors of the second differential pair are of the same polarity.

12. The operational amplifier of claim 10, wherein all transistors of the second differential pair and transistors of the load transistor pair are of the same polarity.

13. The operational amplifier of claim 10, wherein small signal model transconductance of transistors of the first differential pair and small signal model transconductance of transistors of the load transistor pair are substantially fixed relative to each other.

14. The operational amplifier of claim 10, wherein transistors of the second differential pair are PMOS transistors.

15. The operational amplifier of claim 10, wherein transistors of the load transistor pair are PMOS transistors.

16. The operational amplifier of claim 10, further including an amplifier that extends a normal range of operation of the second tail current source transistor.

17. The operational amplifier of claim 10, wherein the current source includes a third differential transistor pair whose gates are driven by the differential input signal.

18. The operational amplifier of claim 10, wherein the first stage includes:

a second differential transistor pair;

a current source connected to sources of the second differential transistor pair; and

a load transistor pair connected in series with the second differential transistor pair.

19. The operational amplifier of claim 10, wherein the first stage expands a common mode input range of the operational amplifier.

11-1. The operational amplifier of claim 10, wherein transistors of the load transistor pair are of the same polarity.