Apparatus and method of parallel processing an MPEG-4 data stream

• US 20040196905A1
• Filed: 04/04/2003
• Published: 10/07/2004
• Est. Priority Date: 04/04/2003
• Status: Active Grant

• Current Assignee: Sony Corporation (Sony Group Corp.), Sony Electronics Inc. (Sony Group Corp.)
• Original Assignee: SONY CORPORATION AND SONY ELECTRONICS INC.
• Inventors: Wang, Jason N., Yamane, Masahito
• Granted Patent: US 7,660,352 B2
• Time in Patent Office: Days
• US Class Current: 375/240.12
• CPC Class Codes: H04N 19/20 using video object coding
• CPC Class Codes: H04N 19/68 involving the insertion of resynchronisation markers into the bitstream
• CPC Class Codes: H04N 19/89 involving methods or arrangements for detection of transmission errors at the decoder

Abstract

An apparatus and method of decoding coded video bitstreams is disclosed. The apparatus comprises a first processor and a second processor configured to operate in parallel. The main processor receives the coded video bitstream, parses it, and calls the second processor to decode the coded video bitstream to retrieve macroblock data. If an error occurs during decoding, the second processor signals the first processor, which can instruct the second processor to perform an error recovery routine. The first processor the performs dequantization and inverse DCT to recover digital pixel data from the macroblocks so that an image formed from the digital pixel data can be later displayed on a monitor.

Claims

1. A data processing system for translating a coded bitstream delimited by a plurality of markers into pixel data suitable for rendering video images, the data processing system comprising:

a. a first processor configured to parse the coded bitstream and divide the coded bitstream into multiple segments delimited by the plurality of markers; and

b. a second processor configured to process a portion of the multiple segments and translate the portion of multiple segments into decoded data elements, wherein the first processor processes the decoded data elements to generate the pixel data and further wherein the first processor and the second processor are configured to operate in parallel.

2. The data processing system of claim 1, wherein the second processor is configured to process variable-length data.

3. The data processing system of claim 2, wherein the second processor comprises a reduced instruction set computer.

4. The data processing system of claim 1, wherein the coded bitstream is a compressed bitstream.

5. The data processing system of claim 4, wherein the compressed bitstream is encoded according to an MPEG standard.

6. The data processing system of claim 5, wherein the MPEG standard is the MPEG-4 standard.

7. The data processing system of claim 4, wherein the compressed bitstream is encoded according to a JPEG standard.

8. The data processing system of claim 4, wherein the compressed bitstream is encoded according to one of the H.261 standard and the H.263 standard.

9. The data processing system of claim 6, wherein the markers are video object plane start codes indicating the start of a video object.

10. The data processing system of claim 6, wherein the decoded data elements comprise macroblocks containing integers representing discrete cosine transform (DCT) coefficients of the pixel data.

11. The data processing system of claim 10, wherein the first processor processing the data elements to generate pixel data comprises:

a. dequantizing the DCT coefficients to generate dequantized DCT coefficients; and

b. performing an inverse DCT transformation on the dequantized DCT coefficients to generate the pixel data.

12. The data processing system of claim 1, further comprising:

a. an external memory configured to store a portion of the coded bitstream and a portion of the decoded data elements; and

b. a high-speed bus coupling the first processor and the second processor to the external memory.

13. The data processing system of claim 12, wherein the first processor comprises a first cache.

14. The data processing system of claim 13, wherein the second processor comprises a second cache.

15. A data processing system for translating a coded bitstream delimited by a plurality of markers into pixel data suitable for rendering video images, the data processing system comprising:

a. a first means for processing configured to parse the coded bitstream and divide the coded bitstream into multiple segments delimited by the plurality of markers; and

b. a second means for processing configured to process a portion of the multiple segments and translate the portion of multiple segments into decoded data elements,

wherein the first means for processing processes the decoded data elements to generate the pixel data and further wherein the first means for processing and the second means for processing are configured to operate in parallel.

16. The data processing system of claim 15, wherein the second means for processing is configured to process variable-length data.

17. The data processing system of claim 16, wherein the second means for processing comprises a reduced instruction set computer.

18. The data processing system of claim 15, wherein the coded bitstream is a compressed bitstream.

19. The data processing system of claim 18, wherein the compressed bitstream is encoded according to an MPEG standard.

20. The data processing system of claim 19, wherein the MPEG standard is the MPEG-4 standard.

21. The data processing system of claim 18, wherein the compressed bitstream is encoded according to a JPEG standard.

22. The data processing system of claim 18, wherein the compressed bitstream is encoded according to one of the H.261 standard and the H.263 standard.

23. The data processing system of claim 20, wherein the markers are video object plane start codes indicating the start of a video object.

24. The data processing system of claim 20, wherein the decoded data elements comprise macroblocks containing integers representing discrete cosine transform (DCT) coefficients of the pixel data.

25. The data processing system of claim 24, wherein the first means for processing processes the data elements to generate pixel data comprises:

a. dequantizing the DCT coefficients to generate dequantized DCT coefficients; and

b. performing an inverse DCT transformation on the dequantized DCT coefficients to generate the pixel data.

26. The data processing system of claim 15, further comprising:

a. an external memory configured to store a portion of the coded bitstream and a portion of the decoded data elements; and

b. a high-speed bus coupling the first means for processing and the second means for processing to the external memory.

27. The data processing system of claim 26, wherein the first means for processing comprises a first cache.

28. The data processing system of claim 27, wherein the second means for processing comprises a second cache.

29. A method of translating a coded bitstream delimited by a plurality of markers into pixel data suitable for rendering video images, the method comprising:

a. dividing the coded bitstream into a plurality of blocks by a first processor, the plurality of blocks comprising compressed data elements delimited by the plurality of markers;

b. parsing in a first direction the compressed data elements by a second processor to translate the compressed data elements into decompressed data elements; and

c. generating the pixel data from the decompressed data elements by the first processor,

wherein the first processor and the second processor are configured to operate in parallel.

30. The method of claim 29, wherein the coded bitstream is coded according to a JPEG standard.

31. The method of claim 29, wherein the coded bitstream is coded according to one of the H.261 standard and the H.263 standard.

32. The method of claim 29, wherein the coded bitstream is coded according to an MPEG standard.

33. The method of claim 32, wherein the MPEG standard is MPEG-4.

34. The method of claim 29, wherein the compressed data elements are Huffman codes of integers representing discrete cosine transform (DCT) coefficients of a video image and the decompressed data elements are the corresponding integers representing discrete cosine transform coefficients of a video image.

35. The method of claim 34, wherein generating the pixel data from the decompressed data elements comprises:

a. dequantizing the DCT coefficients to produce dequantized DCT coefficients; and

b. performing an inverse DCT transformation on the dequantized DCT coefficients to generate the pixel data.

36. The method of claim 35, wherein generating the pixel data from the compressed data elements further comprises performing motion compensation on the dequantized DCT coefficients to generate the pixel data.

37. The method of claim 29, wherein the first processor performs the step of dividing a coded bitstream representing a first video object while the second processor performs the step of translating the compressed data elements into decompressed data elements representing a second video object.

38. The method of claim 37, wherein when an error is encountered during the step of translating the decompressed data elements by a second processor, the second processor transmits an error message to the first processor.

39. The method of claim 38, wherein when the first processor receives the an error message from the second processor, the first processor transmits a start error recovery message to the second processor.

40. The method of claim 39, wherein when the second processor receives a start error recovery message from the first processor, the second processor performs an error recovery routine.

41. The method of claim 40, wherein an error is encountered when an integer in the coded bitstream does not have a corresponding entry in a Huffman table, and further wherein the error recovery routine comprises sequentially parsing in a second direction the compressed data elements and translating the compressed data elements into decompressed data elements corresponding to entries in a reversible Huffman table, the second direction opposite to the first direction.

42. The method of claim 29, wherein translating the compressed data elements comprises sequentially translating the compressed data elements into decompressed data elements using run-length decoding.

43. The method of claim 29, wherein translating the compressed data elements comprises sequentially translating the compressed data elements into decompressed data elements using arithmetic decoding.

44. The method of claim 39, wherein when the first processor receives an error signal from the second processor, the first processor replaces the data elements with data elements corresponding to a third video object different from the second video object.

45. The method of claim 29, wherein the coded bitstream is encoded as partitioned data.

46. The method of claim 29, wherein the markers are resynchronization markers.

47. The method of claim 46, wherein when the second processor encounters an error after parsing a first resynchronization marker, the second processor transmits an error signal to the first processor and continues translating from a second resynchronization marker.

48. A compressed bitstream decoding system for translating a coded compressed bitstream delimited by a plurality of markers into pixel data suitable for rendering video images, the compressed bistream decoding system comprising:

a. a first processor configured to parse the coded compressed bitstream and divide the coded compressed bitstream into multiple segments delimited by the plurality of markers; and

b. a second processor configured to process a portion of the multiple segments and translate the portion of multiple segments into decoded data elements,

wherein the first processor processes the data elements to generate the pixel data and further wherein the first processor and the second processor are configured to operate in parallel.

49. The compressed bitstream decoding system of claim 48, wherein the second processor is configured to process variable-length data.

50. The compressed bitstream decoding system of claim 49, wherein the second processor comprises a reduced instruction set computer.

51. The compressed bitstream decoding system of claim 48, wherein the coded compressed bitstream is encoded according to an MPEG standard.

52. The compressed bitstream decoding system of claim 51, wherein the MPEG standard is the MPEG-4 standard.

53. The compressed bitstream decoding system of claim 48, wherein the coded compressed bitstream is encoded according to a JPEG standard.

54. The compressed bitstream decoding system of claim 48, wherein the coded compressed bitstream is encoded according to one of the H.261 standard and the H.263 standard.

55. The compressed bitstream decoding system of claim 52, wherein the markers are video object plane start codes indicating the start of a video object.

56. The compressed bitstream decoding system of claim 52, wherein the decoded data elements comprise macroblocks containing integers representing discrete cosine transform (DCT) coefficients of the pixel data.

57. The compressed bitstream decoding system of claim 56, wherein the first processor processing the data elements to generate pixel data comprises:

a. dequantizing the DCT coefficients to generate dequantized DCT coefficients; and

b. performing an inverse DCT transformation on the dequantized DCT coefficients to generate the pixel data.

58. The compressed bitstream decoding system of claim 48, further comprising:

a. an external memory configured to store a portion of the coded compressed bitstream and a portion of the decoded data elements; and

b. a high-speed bus coupling the first processor and the second processor to the external memory.

59. The compressed bitstream decoding system of claim 58, wherein the first processor comprises a first cache.

60. The compressed bitstream decoding system of claim 59, wherein the second processor comprises a second cache.

61. A data processing system for processing digital pixel data, comprising:

a. an encoder for encoding the digital pixel data into a coded bistream comprising a plurality of segments delimited by markers;

b. a decoder configured to receive the coded bitstream from the encoder, the decoder comprising a first processor configured to parse the coded bitstream and divide the coded bitstream into multiple segments delimited by the plurality of markers and a second processor configured to process a portion of the multiple segments and translate the portion of multiple segments into decoded data elements,

wherein the first processor processes the decoded data elements to generate the digital pixel data and further wherein the first processor and the second processor are configured to operate in parallel.

62. The data processing system of claim 61, wherein the second processor is configured to process variable-length data.

63. The data processing system of claim 62, wherein the second processor comprises a reduced instruction set computer.

64. The data processing system of claim 61, wherein the compressed bitstream is encoded according to an MPEG standard.

65. The data processing system of claim 64, wherein the MPEG standard is the MPEG-4 standard.

66. The data processing system of claim 61, wherein the compressed bitstream is encoded according to a JPEG standard.

67. The data processing system of claim 61, wherein the compressed bitstream is encoded according to one of the H.261 standard and the H.263 standard.

68. The data processing system of claim 65, wherein the markers are video object plane start codes indicating the start of a video object.

69. The data processing system of claim 65, wherein the decoded data elements comprise macroblocks containing integers representing discrete cosine transform (DCT) coefficients of the pixel data.

70. The data processing system of claim 69, wherein the first processor processing the data elements to generate pixel data comprises:

a. dequantizing the DCT coefficients to generate dequantized DCT coefficients; and

b. performing an inverse DCT transformation on the dequantized DCT coefficients to generate the pixel data.

71. The data processing system of claim 61, further comprising:

a. an external memory configured to store a portion of the coded bitstream and a portion of the decoded data elements; and

b. a high-speed bus coupling the first processor and the second processor to the external memory.

72. The data processing system of claim 71, wherein the first processor comprises a first cache.

73. The data processing system of claim 72, wherein the second processor comprises a second cache.

74. The data processing system of claim 61, further comprising a transmission medium coupling the encoder to the decoder.

75. The data processing system of claim 74, wherein the transmission medium comprises a network.