Method and apparatus for timing recovery in ADSL transceivers under a TCM-ISDN crosstalk environment

• US 20040196938A1
• Filed: 04/19/2004
• Published: 10/07/2004
• Est. Priority Date: 02/29/2000
• Status: Active Grant

• Current Assignee: Ikanos Communications Incorporated (Qualcomm, Inc.)
• Original Assignee: Centillium Communications Incorporated (Transwitch Corporation)
• Inventors: Hung, Chin N., Long, Guozhu, Bar-Ness, Yaron
• Granted Patent: US 7,058,152 B2
• Time in Patent Office: Days
• US Class Current: 375/371
• CPC Class Codes: H04L 27/2662 Symbol synchronisation
• CPC Class Codes: H04L 27/2679 Decision-aided
• CPC Class Codes: H04L 5/1492 with time compression, e.g. operating according to the ping-pong technique

Abstract

A system used to synchronize the clock frequency of a receiver with that of a transmitter, where both the receiver and transmitter communicate using the ADSL Annex C standard. The transmitter continuously transmits pilot tones to the receiver. The receiver determines the phase error between sequential pilot tone symbols to determine a phase error. The receiver uses the phase error to adjust the receiver clock frequency. However, if the most recently received symbol is subject to near end crosstalk or is subject to far end crosstalk and is a boundary symbol, the receiver ignores the phase error and does not adjust the receiver clock frequency.

Claims

1. A computer-implemented method of synchronizing a clock frequency of a receiver with that of a transmitter, the method comprising the acts of:

continuously receiving pilot tone symbols from the transmitter;

determining a phase error between time separated pilot tone symbols;

selectively setting the phase error to zero when the crosstalk environment of the current symbol indicates a noisy environment; and

adjusting the frequency of the receiver clock based on the phase error.

2. The method of claim 1, wherein the act of setting the phase error to zero occurs if the crosstalk is near end type.

3. The method of claim 1, wherein the receiver and transmitter communicate in accordance with ADSL Annex C.

4. An apparatus that determines a phase error to use to synchronize a receiver clock frequency with that of a transmitter, the apparatus comprising:

a transmitter that transmits at least one pilot tone symbol to the receiver;

a sample clock that generates a sample clock signal;

a symbol identifier coupled to receive the sample clock signal and that indicates a symbol index associated with the most recent symbol, the symbol index indicative of the crosstalk environment of the symbol;

a phase error measurer device that measures the phase error between two pilot tone symbols and outputs the phase error; and

a phase error determination device (“

PEDD”

) coupled to receive the phase error from the phase error measurer device and the symbol index from the symbol identifier, wherein the PEDD determines whether to set the phase error to zero based on the crosstalk environment of the most recent symbol, wherein the PEDD adjusts the sample clock signal frequency using the phase error.

5. The apparatus of claim 4, wherein the PEDD determines the crosstalk environment of the most recent symbol by using the symbol index and sets the phase error to zero if the crosstalk environment is near end type.

6. The apparatus of claim 4, wherein the receiver and transmitter communicate in accordance with ADSL Annex C.

7. A computer system adapted for determining a phase error that is used to adjust a clock frequency, the system comprising:

a module for recognizing at least one pilot tone symbol;

a module for indicating a symbol index associated with the most recent symbol, the symbol index indicative of the crosstalk environment of the symbol;

a module for measuring phase error between two pilot tone symbols and for outputting the phase error;

a module for determining whether to set the phase error to zero based on the crosstalk environment of the most recent symbol; and

a module for using the phase error to adjust the clock frequency.

8. The system of claim 7, wherein the module for determining determines the crosstalk environment of the most recent symbol by using the symbol index and sets the phase error to zero if the crosstalk environment is near end type.

9. A computer implemented method for adjusting a clock frequency, the method comprising:

receiving pilot tone symbols;

determining a phase error between time separated pilot tone symbols;

selectively setting the phase error to zero when the crosstalk environment of the current symbol indicates a noisy environment; and

adjusting the frequency of the clock based on the phase error.

10. The method of claim 9, wherein the act of setting the phase error to zero occurs if the crosstalk is near end type.

11. A computer program product for adjusting a clock frequency, the computer program product comprising a computer-readable medium containing computer program code for performing the operations:

recognizing pilot tone symbols;

determining a phase error between time separated pilot tone symbols;

selectively setting the phase error to zero when the crosstalk environment of the current symbol indicates a noisy environment; and

adjusting the clock frequency based on the phase error.

12. The computer program product of claim 11, wherein selectively setting comprises setting the phase error to zero if the crosstalk is near end type.