Synchronous flash memory with status burst output

• US 20040199713A1
• Filed: 04/26/2004
• Published: 10/07/2004
• Est. Priority Date: 07/28/2000
• Status: Active Grant

• Current Assignee: Round Rock Research LLC
• Original Assignee: Micron Technology, Inc.
• Inventors: Roohparvar, Frankie F.
• Granted Patent: US 7,096,283 B2
• Time in Patent Office: Days
• US Class Current: 711/103
• CPC Class Codes: G11C 16/20 Initialising; Data preset; Chip identification
• CPC Class Codes: G11C 16/22 Safety or protection circuits preventing unauthorised or accidental access to memory cells
• CPC Class Codes: G11C 16/26 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 7/1018 Serial bit line access mode, e.g. using bit line address shift registers, bit line address counters, bit line burst counters
• CPC Class Codes: G11C 7/103 using serially addressed read-write data registers G11C7/1036 takes precedence
• CPC Class Codes: G11C 7/1072 for memories with random access ports synchronised on clock signal pulse trains, e.g. synchronous memories, self timed memories

Abstract

A synchronous flash memory includes an array of non-volatile memory cells. The memory array is arranged in rows and columns, and can be further arranged in addressable blocks. Data communication connections are used for bidirectional data communication with an external device(s), such as a processor or other memory controller. The memory can output data from storage registers on the data communication connections during a series of clock cycles to provide a burst of register data. The memory can also provide the register data in accordance to a defined clock latency value. The register data can include status data, operating setting data, manufacture identification, and memory device identification.

Claims

1. A method of operating a synchronous memory device comprising:

establishing a read burst length of x-cycles such that data output from the synchronous memory device is output on x-consecutive clock cycles;

initiating a register read operation to read data stored in an internal register; and

outputting data stored in the internal register on external data connections for x-consecutive clock cycles.

2. The method of claim 1 further comprises establishing a clock latency of y-cycles, such that the data stored in the internal registers is output y-clock cycles following the initiation of the register read.

3. The method of claim 1 wherein the internal register contains operating data, status data, manufacture identification, or memory device identification.

4. A method of operating a synchronous memory device comprising:

receiving a read register command; and

outputting register data from the synchronous memory device in response to the read register command for x-clock cycles.

5. The method of claim 4 wherein the synchronous memory device is a synchronous flash memory device having non-volatile memory cells.

6. The method of claim 4 wherein the register data is output y-clock cycles after receiving the read register command.

7. The method of claim 4 wherein the register data comprises operating data, status data, manufacture identification, or memory device identification.

8. The method of claim 4 wherein x-clock cycles is selected from either 2, 4, 8 or 16 clock cycles.

9. A method of reading register data in a synchronous memory device comprising:

providing a register read command from a processor to the memory device;

receiving the register read command on an input of the memory device on a first clock cycle;

reading register data stored in a memory register;

outputting the register data during a plurality of clock cycles on data communication connections of the synchronous memory device, wherein outputting the register data is delayed for a predefined clock latency period after receiving the register read command.

10. The method of claim 9 wherein the register data comprises operating data, status data, manufacture identification, or memory device identification.

11. The method of claim 9 further comprises:

setting a burst length of the synchronous memory device to define the plurality of clock cycles that the register data is output; and

setting a clock latency period.

12. The method of claim 11 wherein the burst length is selected from either 2, 4, 8 or 16 clock cycles.

13. The method of claim 9 wherein the synchronous memory device is a synchronous flash memory device having non-volatile memory cells.

14. A method of operating to a synchronous memory device comprising:

executing a write operation on an array of the memory device;

providing a register read command from a processor to the memory device during the execution of the write operation;

receiving the register read command on an input of the memory device on a first clock cycle;

reading register data stored in a memory register;

outputting the register data during a plurality of clock cycles on data communication connections of the synchronous memory device, wherein outputting the register data is delayed for a predefined clock latency period after receiving the register read command.

15. The method of claim 14 wherein the register data indicates a write status of the memory device.

16. The method of claim 14 further comprises:

setting a burst length of the synchronous memory device to define the plurality of clock cycles that the register data is output; and

setting a clock latency period.

17. A method of operating a synchronous memory device, comprising:

programming a read register with a burst length setting and clock latency setting;

placing the memory in a register read mode; and

outputting register data for a series of clock cycles according to the read register programming.

18. The method of claim 17, wherein outputting further comprises:

controlling register data output using the burst length setting and the closk latency setting of the programming.

19. The method of claim 17, and further comprising:

providing a memory status signal from a status reguster upon initiation of a status read command.

20. The method of claim 17, wherein the burst length setting is four words and the clock latency setting is three cycles.