Transceiver circuit, transceiving method, and transceiver apparatus
First Claim
1. A transceiver circuit capable of transferring data at one or more transfer rates, the transceiver circuit comprising:
- one or more state machines having one or more tone phases in which determination of the maximum transfer rate for one or more channels and one or more connections with one or more remote devices is carried out through exchange of one or more tone signals with at least one of the remote device or devices, and one or more data transfer phases in which data transfer is carried out at one or more frequencies higher than that of at least one of the tone signal or signals;
one or more error detection circuits detecting one or more errors in one or more receive signals; and
one or more data transfer phase transition suppressor circuits;
wherein, in the event that at least one of the error detection circuit or circuits detects at least one of the error or errors within at least one of the receive signal or signals during at least one of the data transfer phase or phases, one or more transitions is made from at least one of the data transfer phase or phases to at least one of the tone phase or phases, and after at least one of such transition or transitions has occurred, at least one of the data transfer phase transition suppressor circuit or circuits carries out control so as to prevent transition back to at least one of the data transfer phase or phases.
1 Assignment
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Accused Products
Abstract
A transceiver circuit comprising state machine(s) having tone phase(s) and data transfer phase(s), error detection circuit(s) detecting error(s) in receive signal(s), and phase transition suppressor circuit(s); wherein, in the event that it is determined as a result of error detection that channel quality is so poor as to make it impossible to carry out normal data transfer, transition may be made from data transfer phase(s) to tone phase(s), and by thereafter preventing transition back to data transfer phase(s) and/or speed negotiation phase(s), power consumption as would be consumed by high-speed circuit(s) when in data transfer phase(s) and/or speed negotiation phase(s) may be reduced or eliminated. Furthermore, by suppressing generation of BUS_RESET(s) due to error(s) during data transfer phase(s), reduction in bus power consumption and/or improved bus stability may be achieved.
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Citations
39 Claims
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1. A transceiver circuit capable of transferring data at one or more transfer rates, the transceiver circuit comprising:
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one or more state machines having one or more tone phases in which determination of the maximum transfer rate for one or more channels and one or more connections with one or more remote devices is carried out through exchange of one or more tone signals with at least one of the remote device or devices, and one or more data transfer phases in which data transfer is carried out at one or more frequencies higher than that of at least one of the tone signal or signals;
one or more error detection circuits detecting one or more errors in one or more receive signals; and
one or more data transfer phase transition suppressor circuits;
wherein, in the event that at least one of the error detection circuit or circuits detects at least one of the error or errors within at least one of the receive signal or signals during at least one of the data transfer phase or phases, one or more transitions is made from at least one of the data transfer phase or phases to at least one of the tone phase or phases, and after at least one of such transition or transitions has occurred, at least one of the data transfer phase transition suppressor circuit or circuits carries out control so as to prevent transition back to at least one of the data transfer phase or phases. - View Dependent Claims (2, 3, 9, 10, 11, 12, 13, 14, 27, 28, 29, 30, 31, 32, 36, 38, 39)
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4. A transceiver circuit capable of transferring data at one or more transfer rates, the transceiver circuit comprising:
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one or more state machines having one or more tone phases in which one or more connections with one or more remote devices are established through exchange of one or more tone signals with at least one of the remote device or devices, one or more speed negotiation phases in which determination of the maximum transfer rate permitted by one or more channels is carried out through mutual notification of one or more transfer rates of which the local device is capable, this notification being actually carried out at at least one of such transfer rate or rates, and one or more data transfer phases in which data transfer is carried out at at least one of the transfer rate or rates determined at at least one of the speed negotiation phase or phases;
one or more error detection circuits detecting one or more errors in one or more receive signals; and
one or more speed negotiation phase transition suppressor circuits;
wherein, in the event that at least one of the error detection circuit or circuits detects at least one of the error or errors within at least one of the receive signal or signals during at least one of the data transfer phase or phases, one or more transitions is made from at least one of the data transfer phase or phases to at least one of the tone phase or phases, and after at least one of such transition or transitions has occurred, at least one of the speed negotiation phase transition suppressor circuit or circuits carries out control so as to prevent transition to at least one of the speed negotiation phase or phases. - View Dependent Claims (6, 7, 8, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 37)
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5. A transceiver circuit capable of transferring data at one or more transfer rates, the transceiver circuit comprising:
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one or more state machines having one or more tone phases in which one or more connections with one or more remote devices are established through exchange of one or more tone signals with at least one of the remote device or devices, one or more speed negotiation phases in which determination of one or more maximum transfer rates permitted by one or more channels is carried out through mutual notification of one or more transfer rates of which the local device is capable, this notification being actually carried out at at least one of such transfer rate or rates, and one or more data transfer phases in which data transfer is carried out at at least one of the transfer rate or rates determined at at least one of the speed negotiation phase or phases;
one or more error detection circuits detecting one or more errors in one or more receive signals; and
one or more speed negotiation phase transition suppressor circuits;
wherein, in the event that at least one of the error detection circuit or circuits detects at least one of the error or errors within at least one of the receive signal or signals during at least one of the speed negotiation phase or phases, one or more transitions is made from at least one of the data transfer phase or phases to at least one of the tone phase or phases, and after at least one of such transition or transitions has occurred, at least one of the speed negotiation phase transition suppressor circuit or circuits carries out control so as to prevent transition to at least one of the speed negotiation phase or phases.
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33. A transceiver circuit capable of transferring data at a plurality of transfer rates, the transceiver circuit comprising:
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one or more state machines having one or more tone phases in which one or more connections with one or more remote devices are established through exchange of one or more tone signals with at least one of the remote device or devices, one or more speed negotiation phases in which determination of the maximum transfer rate permitted by one or more channels is carried out through mutual notification of one or more transfer rates of which one or more local devices is capable, this notification being actually carried out at at least one of such transfer rate or rates, and one or more data transfer phases in which data transfer is carried out at at least one of the transfer rate or rates determined at at least one of the speed negotiation phase or phases;
one or more error detection circuits detecting one or more errors in one or more receive signals; and
one or more transfer rate comparison circuits comparing the minimum transfer rate of the transceiver circuit and one or more transfer rates employed during at least one of the data transfer phase or phases;
wherein, in the event that at least one of the error detection circuit or circuits detects at least one of the error or errors within at least one of the receive signal or signals during at least one of the data transfer phase or phases when at least one result of at least one comparison made by at least one of the transfer rate comparison circuit or circuits is that at least one of the transfer rate or rates employed during at least one of the data transfer phase or phases is greater than the minimum transfer rate or rates of the transceiver circuit, one or more transitions is made from at least one of the data transfer phase or phases to at least one of the tone phase or phases, and thereafter, the maximum transfer rate of the transceiver circuit during at least one of the speed negotiation phase or phases is set so as to be at least one rate that is lower than at least one transfer rate employed during at least one of the data transfer phase or phases. - View Dependent Claims (34, 35)
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Specification