Test system with high accuracy time measurement system

• US 20040199842A1
• Filed: 04/04/2003
• Published: 10/07/2004
• Est. Priority Date: 04/04/2003
• Status: Abandoned Application

• Current Assignee: Teradyne Incorporated
• Original Assignee: Teradyne Incorporated
• Inventors: Sartschev, Ronald A.
• Application Number:
  US10/407,769
• Publication Number:
  US 20040199842A1
• Time in Patent Office: Days
• US Class Current: 714/731
• CPC Class Codes: G01R 31/2882 Testing timing characteristics
• CPC Class Codes: G01R 31/3016 Delay or race condition test, e.g. race hazard test
• CPC Class Codes: G01R 31/31937 Timing aspects, e.g. measuring propagation delay G01R31/3191 and G01R31/31922 take precedence; marginal testing G06F11/24
• CPC Class Codes: G04F 10/00 Apparatus for measuring unknown time intervals by electric means

Abstract

An automatic test system for testing semiconductor devices. The test system includes time measurement circuitry. The time measurement circuitry can be programmed to operate in a single-shot mode or a higher resolution, repetitive-measurement mode. To simplify the design and construction of the system, the same time measurement circuit is used in both measurement modes. To provide higher resolution in the repetitive measurement mode, variation is introduced into the signal to be measured and resulting measurements are averaged. Any bias introduced by the variation is subtracted from the averaged value.

Claims

1. A method of operating an automatic test system of the type having a time measurement circuit characterized in that the time measurement circuit has a mode of operation for repetitive events to increase the resolution of the time measurements comprising:

a) introducing time variation into the signal before measuring the timing of an event within the signal;

b) repetitively measuring the timing of the event within the signal;

c) averaging the time measurements to thereby determine the timing of the event in a resolution greater than the resolution of the time measurements.

2. The method of operating an automatic test system of claim 1 additionally comprising disabling the introduction of variation into the signal when making a single shot measurement.

3. The method of operating an automatic test system of claim 1 wherein the measuring the timing of an event within the signal is performed with circuitry in a CMOS integrated circuit.

4. The method of operating an automatic test system of claim 3 wherein introducing variation into the signal is controlled by CMOS circuitry in the CMOS integrated circuit.

5. The method of claim 1 wherein the introduced variation adds a known bias to the signal and the step of determining the timing of the event comprises subtracting the known bias from the average of the time measurements.

6. The method of claim 1 wherein introducing variation comprises passing the signal through a variable delay element and varying the delay of the delay element.

7. The method of claim 6 wherein the variable delay element comprises a plurality of capacitors switchably coupled to the signal path and the delay is varied by altering the number of capacitors switched to the signal path.

8. The method of claim 6 wherein the delay through the delay element is varied by a control signal generated by retrieving values from a memory circuit.

9. The method of claim 6 wherein the variable delay is a differential delay.

10. The method of claim 9 wherein the variable delay comprises an input buffer and an output buffer amplifier, with a pair of signal lines running therebetween with a plurality of pairs of matched capacitors, with a capacitor in each of the pairs switchably connectable to one of the signal lines in the pair.

11. The method of claim 1 used to manufacture semiconductor chips,

a) wherein the signal is generated by a semiconductor chip being manufactured;

and

b) the method additionally comprises;

i) comparing the determined timing of the signal to a predetermined value;

ii) selecting additional processing steps to be performed on the semiconductor chip in response to the comparison made on the determined timing.

12. An automatic test system of the type having a time measurement circuit characterized in that the time measurement circuit has a mode of operation for repetitive events to increase the resolution of the time measurements, operated according to a method comprising:

a) introducing time variation into the signal before measuring the timing of an event within the signal;

b) repetitively measuring the timing of the event within the signal;

c) averaging the time measurements to thereby determine the timing of the event in a resolution greater than the resolution of the time measurements.

13. The automatic test system of claim 12 operated according to a method additionally comprising disabling the introduction of variation into the signal when making a single shot measurement.

14. The automatic test system of claim 12 comprising a CMOS integrated circuit adapted to measure the timing of an event within the signal.

15. The automatic test system of claim 14 wherein circuitry within the CMOS integrated circuit is adapted to introduce variation into the signal.

16. The automatic test system of claim 12 additionally comprising a variable delay element adapted for introducing variation into the signal.

17. The automatic test system of claim 16 wherein the variable delay element comprises a plurality of capacitors switchably coupled to the signal path and the delay is varied by altering the number of capacitors switched to the signal path.

18. The automatic test system of claim 16 wherein the delay through the delay element is varied by a control signal generated by retrieving values from a memory circuit.

19. A CMOS integrated circuit chip adapted to increase the resolution of repetitive measurements in an automatic test system, comprising:

a) a time stamp circuit having an input and an output, the output representing time measurements with a first predetermined resolution;

b) a variable delay element connected to the input of the time stamp circuit;

c) an averaging circuit connected to the output of the time stamp circuit having an input coupled to the output of the time stamp circuit and an output providing time measurements with a second resolution, greater than the first predetermined resolution.

20. The CMOS integrated circuit chip of claim 19 additionally comprising a delay control circuit having an output coupled to and controlling the variable delay element, the delay control circuit generating as an output a periodic signal.