Very low temperature CVD process with independently variable conformality, stress and composition of the CVD layer

• US 20040200417A1
• Filed: 05/03/2004
• Published: 10/14/2004
• Est. Priority Date: 06/05/2002
• Status: Active Grant

• Current Assignee: Applied Materials Incorporated
• Original Assignee: Applied Materials Incorporated
• Inventors: Ramaswamy, Kartik, Hanawa, Hiroji, Collins, Kenneth S., Nguyen, Andrew, Al-Bayati, Amir, Gallo, Biagio
• Granted Patent: US 7,223,676 B2
• Time in Patent Office: Days
• US Class Current: 118/723I
• CPC Class Codes: C23C 14/48 Ion implantation
• CPC Class Codes: C23C 16/507 using external electrodes, e.g. in tunnel type reactors
• CPC Class Codes: H01J 2237/2001 Maintaining constant desired temperature
• CPC Class Codes: H01J 37/321 the radio frequency energy being inductively coupled to the plasma
• CPC Class Codes: H01J 37/32174 Circuits specially adapted for controlling the RF discharge
• CPC Class Codes: H01J 37/32357 Generation remote from the workpiece, e.g. down-stream
• CPC Class Codes: H01J 37/32412 Plasma immersion ion implantation
• CPC Class Codes: H01L 21/02126 the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
• CPC Class Codes: H01L 21/02274 in the presence of a plasma [PECVD]
• CPC Class Codes: H01L 21/2236 from or into a plasma phase
• CPC Class Codes: H01L 21/26513 of electrically active species
• CPC Class Codes: H01L 21/2658 of a molecular ion, e.g. decaborane
• CPC Class Codes: H01L 21/31604 Deposition from a gas or vapour H01L21/31691, H01L21/31695 take precedence
• CPC Class Codes: H01L 21/318 composed of nitrides
• CPC Class Codes: H01L 21/823807 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 21/823814 with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
• CPC Class Codes: H01L 21/823842 gate conductors with different gate conductor materials or different gate conductor implants, e.g. dual gate structures
• CPC Class Codes: H01L 29/6659 with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
• CPC Class Codes: Y10T 29/5313 Means to assemble electrical device

Abstract

A low temperature process for depositing a coating containing any of silicon, nitrogen, hydrogen or oxygen on a workpiece includes placing the workpiece in a reactor chamber facing a processing region of the chamber, introducing a process gas containing any of silicon, nitrogen, hydrogen or oxygen into the reactor chamber, generating a torroidal RF plasma current in a reentrant path through the processing region by applying RF plasma source power at an HF frequency on the order of about 10 MHz to a portion of a reentrant conduit external of the chamber and forming a portion of the reentrant path, applying RF plasma bias power at an LF frequency on the order of one or a few MHz to the workpiece, and maintaining the temperature of the workpiece under about 100 degrees C.

Claims

1-35. -35. (canceled)

36. A low temperature process for depositing a coating containing any of a semiconductor element, nitrogen, hydrogen or oxygen on a workpiece, said process comprising:

placing the workpiece in a reactor chamber facing a processing region of the chamber;

introducing a process gas containing any of a semiconductor element, nitrogen, hydrogen or oxygen into the reactor chamber;

generating a torroidal RF plasma current in a reentrant path through the processing region by applying RF plasma source power at a first frequency to a portion of a reentrant conduit external of the chamber and forming a portion of the reentrant path; and

maintaining the temperature of the workpiece under about 100 degrees C.

37. The process of claim 36 further comprising applying an RF plasma bias voltage at a second frequency to the workpiece.

38. The process of claim 37 wherein said RF plasma source power is in a range of about 100 Watts to on the order of about 10 kiloWatts.

39. The process of claim 38 wherein said RF plasma bias voltage corresponds to a bias power in a range of zero to about 10 kilowatts.

40. The process of claim 36 further comprising:

setting conformality of the coating within a range between conformal and non-conformal and while setting stress in the coating within a range between compressive stress and tensile stress.

41. The process of claim 40 wherein:

the step of setting conformality comprises setting said RF plasma source power at a level anywhere within a range between a maximum source power at which the coating is deposited conformally and a minimum source power at which the coating is deposited non-conformally; and

the step of setting stress comprises controlling the stress by applying an RF bias voltage corresponding to a desired level of stress.

42. The process of claim 41 wherein the step of controlling the stress with an RF bias voltage comprises applying an RF bias voltage to said workpiece corresponding to a bias power level anywhere within a range between a maximum bias power at which the coating is deposited with a compressive stress and a minimum or zero bias power at which the coating is deposited with a tensile stress.

43. The process of claim 42 wherein said maximum source power is on the order of about 10 kiloWatts and said minimum source power is on the order of about 100 Watts.

44. The process of claim 42 wherein said maximum bias power is on the order of about 10 kiloWatts and said minimum bias power is about zero.

45. The process of claim 44 wherein said maximum source power corresponds to a conformality ratio in excess of about 0.5 and said minimum source power corresponds to a conformality ratio not exceeding about 0.1.

46. The process of claim 42 wherein said minimum bias power corresponds to a stress level in the coating of about +1 gigapascal and said maximum bias power corresponds to a stress level in the coating of about −

1 gigaPascal.

47. The process of claim 36 further comprising:

pre-treating the chamber by coating interior surfaces of the chamber with a coating containing at least one of silicon, nitrogen, hydrogen or oxygen prior to placing the workpiece in the chamber.

48. The process of claim 36 further comprising:

performing a post deposition ion implantation process on the workpiece in the chamber after the deposition of the coating is complete, by generating in the reentrant path a torroidal RF plasma current comprising ions to be implanted and applying a bias voltage to the workpiece corresponding to a desired ion implantation depth.

49. The process of claim 48 wherein said post deposition ion implantation process comprises:

ion bombarding the workpiece with ions having a kinetic energy corresponding to an implant depth at the level of the interface between the coating and an underlying layer of the workpiece on which the coating was deposited, so as to enhance the adhesion of the coating.

50. The process of claim 48 wherein said post deposition ion implantation process comprises:

implanting ions in the coating of a selected species so as to enrich the content of said species in the coating.

51. The process of claim 50 wherein said content is enriched beyond a stochiometric ratio.

52. The process of claim 50 wherein said selected species comprises nitrogen, whereby said post deposition ion implantation process enhances the dielectric constant of the coating.

53. The process of claim 50 wherein said selected species comprises hydrogen, whereby said post deposition ion implantation process adjusts the stress of the coating.

54. The process of claim 48 wherein said post deposition ion implantation process comprises:

implanting ions in the coating of a selected species not compatible with plasma chemical vapor deposition.

55. The process of claim 54 wherein said selected species comprises one of:

(a) oxygen gas, (b) fluorine gas.

56. The process of claim 48 further comprising a flash anneal step having at least one of:

(a) a sufficiently low temperature, (b) a sufficiently short duration, to limit a diffusion length in the workpiece below a feature size on the order of tens of nanometers.

57. The process of claim 36 wherein the workpiece has a high aspect ratio opening which the coating is to fill, said process further comprising:

employing a nitrogen-containing process gas at the beginning of the deposition process.

58. The process of claim 57 further comprising:

increasing the oxygen content of the process gas as the high aspect ratio opening begins to fill up with the coating, while decreasing the nitrogen content of said process gas, until at least nearly all of the nitrogen content has been replaced by oxygen content when the high aspect ratio opening is at least nearly filled with the coating.

59. The process of claim 58 wherein said plasma source power level is set to produce a non-conformal coating.

60. The process of claim 58 wherein said plasma source power level is set of produce an at least nearly conformal coating.

61. The reactor of claim 36 wherein said first frequency is about an order of magnitude greater than said second frequency.

62. The reactor of claim 36 wherein said first frequency is an HF frequency and said second frequency is an LF frequency.

63. The reactor of claim 36 wherein said first frequency is on the order of ten or tens of MHz and said second frequency is on the order of one or a few MHz.

64. The process of claim 36 wherein said semiconductor element comprises silicon.

65. The process of claim 37 wherein said first and second frequencies are the same frequency.

66. A method of forming device enhancing coatings on a workpiece having complementary metal oxide semiconductor (CMOS) devices consisting of a set of N-channel devices and a set of P-channel devices, said method comprising:

successively masking with photoresist each one of the sets of N-channel and P-channel devices while unmasking or leaving unmasked the other set, and after each step of successively masking one of the sets of devices, carrying out the following deposition steps;

placing the workpiece in a reactor chamber facing a processing region of the chamber;

introducing a process gas containing any of a semiconductor element, nitrogen, hydrogen or oxygen into the reactor chamber;

generating a torroidal RF plasma current in a reentrant path through the processing region by applying RF plasma source power at a first frequency to a region of a reentrant conduit external of the chamber and forming a portion of the reentrant path;

applying an RF plasma bias voltage at a second frequency to the workpiece;

maintaining the temperature of the workpiece below a threshold photoresist removal temperature;

setting said RF plasma source power at a level at which the coating is deposited non-conformally; and

setting said RF bias voltage at a level at which the coating is deposited with a first stress when the unmasked set consists of the P-channel devices and with a second stress when the unmasked set consists of N-channel devices.

67. The method of claim 66 wherein said first stress is a compressive stress and said second stress is a tensile stress.

68. The method of claim 66 further comprising:

following removal of photoresist from the workpiece, coating the workpiece with a passivation layer having zero stress and high conformality by setting said RF plasma bias voltage for low or at least nearly zero stress and setting said RF plasma source power for maximum conformality while continuing to generate said RF torroidal plasma current.

69. The reactor of claim 66 wherein said first frequency is about an order of magnitude greater than said second frequency.

70. The reactor of claim 66 wherein said first frequency is an HF frequency and said second frequency is an LF frequency.

71. The reactor of claim 66 wherein said first frequency is on the order of ten or tens of MHz and said second frequency is on the order of one or a few MHz.

72. The process of claim 66 wherein said semiconductor element comprises silicon.

73. A method of forming device enhancing coatings on a workpiece having complementary metal oxide semiconductor (CMOS) devices consisting of a set of N-channel devices and a set of P-channel devices, said method comprising:

placing a first photoresist mask over one of the sets of N-channel and P-channel devices while leaving the other set exposed,

placing the workpiece in a reactor chamber facing a processing region of the chamber;

introducing a process gas containing any of a semiconductor element, nitrogen, hydrogen or oxygen into the reactor chamber;

generating a torroidal RF plasma current in a reentrant path through the processing region by applying RF plasma source power at a first frequency to a portion of an external conduit forming a portion of the reentrant path;

applying an RF plasma bias voltage at a second frequency to the workpiece;

maintaining the temperature of the workpiece under a threshold temperature below which the photoresist mask is not destroyed;

setting said RF plasma source power at a level at which the coating is deposited with a first value of conformality lying in a range between maximum conformality and maximum non-conformality;

setting said RF bias voltage at a level at which the coating is deposited with a first stress if the one set consists of the P-channel devices and with a second stress if the one set consists of N-channel devices;

removing the first photoresist mask and placing a second photoresist mask over the other of the sets of N-channel and P-channel devices,

setting said RF plasma source power at a level at which the coating is deposited with a second value of conformality lying in a the range between minimum conformality and maximum non-conformality;

setting said RF bias voltage at a level at which the coating is deposited with a first stress if the other set consists of the P-channel devices and with a second stress if the other set consists of N-channel devices.

74. The method of claim 73 wherein said first value of conformality corresponds to a non-conformal coating, said second value of conformality corresponds to a conformal coating, said first stress is a compressive stress and said second stress is a tensile stress.

75. The method of claim 73 further comprising:

removing said second photoresist mask;

coating the workpiece with a passivation layer having zero stress and high conformality by setting said RF plasma bias voltage for zero stress and setting said RF plasma source power for maximum conformality while continuing to generate said RF torroidal plasma current.

76. The reactor of claim 73 wherein said first frequency is about an order of magnitude greater than said second frequency.

77. The reactor of claim 73 wherein said first frequency is an HF frequency and said second frequency is an LF frequency.

78. The reactor of claim 73 wherein said first frequency is on the order of ten or tens of MHz and said second frequency is on the order of one or a few MHz.

79. The process of claim 73 wherein said semiconductor element comprises silicon.

80. A method of forming a device enhancing coating on a workpiece having complementary metal oxide semiconductor (CMOS) devices consisting of a set of N-channel devices and a set of P-channel devices, said method comprising:

placing the workpiece in a reactor chamber facing a processing region of the chamber;

introducing a process gas containing any of a semiconductor element, nitrogen, hydrogen or oxygen into the reactor chamber;

generating a torroidal RF plasma current in a reentrant path through the processing region by applying RF plasma source power at a first frequency to a portion of an external conduit forming a portion of the reentrant path;

applying an RF plasma bias voltage at a second frequency to the workpiece;

maintaining the temperature of the workpiece under a threshold temperature below which the photoresist mask is not destroyed;

setting said RF bias voltage at a level lying within a range including zero volts at which the coating is deposited with one of;

(a) compressive stress, (b) tensile stress;

placing a photoresist mask over one of (a) the N-channel devices, (b) the P-channel devices, respectively,

ion implanting into the exposed portion of the coating at least one of hydrogen and helium with sufficient bias voltage and implant dose to transform the stress in said exposed portion from one of (a) compressive, (b) tensile, to the other.

81. The process of claim 80 wherein said semiconductor element comprises silicon.

82. A process for depositing a coating containing any of a semiconductor element, nitrogen, hydrogen or oxygen on a workpiece, said process comprising:

placing the workpiece in a reactor chamber facing a processing region of the chamber;

introducing a process gas containing any of a semiconductor element, nitrogen, hydrogen or oxygen into the reactor chamber;

generating a torroidal RF plasma current in each of a pair of mutually transverse reentrant paths passing through and intersecting one another in the processing region by applying RF plasma source power at a first frequency to a portion of a reentrant conduit external of the chamber and forming a portion of the reentrant path.

83. The process of claim 82 further comprising applying an RF bias voltage at a second frequency.

84. The process of claim 82 wherein said RF plasma source power is in a range of about 100 Watts to on the order of about 10 kilowatts.

85. The process of claim 84 wherein said RF plasma bias voltage corresponds to a bias power in a range of zero to about 10 kilowatts.

86. The process of claim 82 further comprising:

setting conformality of the coating within a range between conformal and non-conformal and while setting stress in the coating within a range between compressive stress and tensile stress.

87. The process of claim 86 wherein:

the step of setting conformality comprises setting said RF plasma source power at a level anywhere within a range between a maximum source power at which the coating is deposited conformally and a minimum source power at which the coating is deposited non-conformally; and

the step of setting stress comprises applying an RF bias voltage at a level corresponding to a bias power level anywhere within a range between a maximum bias power at which the coating is deposited with a compressive stress and a minimum bias power at which the coating is deposited with a tensile stress, said minimum bias power lying within a range including zero power.

88. The process of claim 87 wherein said maximum source power is on the order of about 10 kilowatts and said minimum source power is on the order of about 100 Watts.

89. The process of claim 87 wherein said maximum bias power is on the order of about 10 kiloWatts and said minimum bias power is about zero.

90. The process of claim 87 wherein said maximum source power corresponds to a conformality ratio in excess of about 0.5 and said minimum source power corresponds to a conformality ratio not exceeding about 0.1.

91. The process of claim 87 wherein said minimum bias power corresponds to a stress level in the coating of about +1 gigaPascal and said maximum bias power corresponds to a stress level in the coating of about −

1 gigapascal.

92. The process of claim 82 further comprising:

pre-treating the chamber by coating interior surfaces of the chamber with a coating containing at least one of silicon, nitrogen, hydrogen or oxygen prior to placing the workpiece in the chamber.

93. The process of claim 82 further comprising:

performing a post deposition ion implantation process on the workpiece in the chamber after the deposition of the coating is complete, by generating in the reentrant path a torroidal RF plasma current comprising ions to be implanted and applying a bias voltage to the workpiece corresponding to a desired ion implantation depth.

94. The process of claim 93 wherein said post deposition ion implantation process comprises:

ion bombarding the workpiece with ions having a kinetic energy corresponding to an implant depth at the level of the interface between the coating and an underlying layer of the workpiece on which the coating was deposited, so as to enhance the adhesion of the coating.

95. The process of claim 93 wherein said post deposition ion implantation process comprises:

implanting ions in the coating of a selected species so as to enrich the content of said species in the coating.

96. The process of claim 95 wherein said content is enriched beyond a stochiometric ratio.

97. The process of claim 95 wherein said selected species comprises nitrogen, whereby said post deposition ion implantation process enhances the dielectric constant of the coating.

98. The process of claim 95 wherein said selected species comprises hydrogen, whereby said post deposition ion implantation process adjusts the stress of the coating.

99. The process of claim 93 wherein said post deposition ion implantation process comprises:

implanting ions in the coating of a selected species not compatible with plasma chemical vapor deposition.

100. The process of claim 99 wherein said selected species comprises one of:

(a) oxygen gas, (b) fluorine gas.

101. The process of claim 93 further comprising a flash anneal step having at least one of:

(a) a sufficiently low temperature, (b) a sufficiently short duration, to limit a diffusion length in the workpiece below a feature size on the order of tens of nanometers.

102. The process of claim 82 wherein the workpiece has a high aspect ratio opening which the coating is to fill, said process further comprising:

employing a nitrogen-containing process gas at the beginning of the deposition process.

103. The process of claim 102 further comprising:

increasing the oxygen content of the process gas as the high aspect ratio opening begins to fill up with the coating, while decreasing the nitrogen content of said process gas, until at least nearly all of the nitrogen content has been replaced by oxygen content when the high aspect ratio opening is at least nearly filled with the coating.

104. The process of claim 102 wherein said plasma source power level is set to produce a non-conformal coating.

105. The process of claim 103 wherein said plasma source power level is set of produce a conformal coating.

106. The reactor of claim 83 wherein said first frequency is about an order of magnitude greater than said second frequency.

107. The reactor of claim 83 wherein said first frequency is an HF frequency and said second frequency is an LF frequency.

108. The reactor of claim 83 wherein said first frequency is on the order of ten or tens of MHz and said second frequency is on the order of one or a few MHz.

109. The process of claim 83 wherein said first and second frequencies are the same frequency.

110. The process of claim 82 wherein said semiconductor element comprises silicon.

111. A process for depositing a coating containing any of a semiconductor element, nitrogen, hydrogen or oxygen on a workpiece, said process comprising:

placing the workpiece in a reactor chamber facing a processing region of the chamber;

introducing a process gas containing any of a semiconductor element, nitrogen, hydrogen or oxygen into the reactor chamber through a gas distribution plate overlying said processing region;

generating a torroidal RF plasma current in a reentrant path that extends around said gas distribution plate and across said processing region by applying RF plasma source power at a first frequency to a portion of a reentrant conduit external of the chamber and forming a portion of the reentrant path.

112. The process of claim 111 further comprising applying an RF plasma bias voltage at a second frequency.

113. The process of claim 111 wherein said semiconductor element comprises silicon.

114. A process for depositing a coating containing any of a semiconductor element, nitrogen, hydrogen or oxygen on a workpiece, said process comprising:

placing the workpiece in a reactor chamber facing a processing region of the chamber;

introducing a process gas containing any of a semiconductor element, nitrogen, hydrogen or oxygen into the reactor chamber;

generating a torroidal RF plasma current in a reentrant path passing outside of said chamber and across the processing region by applying RF plasma source power at a first frequency to a portion of a reentrant conduit external of the chamber and forming a portion of the reentrant path;

restricting a cross-sectional area of the portion of said reentrant path within said processing region relative to the remaining portion of said reentrant path.

115. The process of claim 114 further comprising applying an RF plasma bias voltage at a second frequency.