Resin sealing-type semiconductor device and method for manufacturing the same

• US 20040201082A1
• Filed: 03/04/2004
• Published: 10/14/2004
• Est. Priority Date: 03/05/2003
• Status: Active Grant

• Current Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Original Assignee: Kanto Sanyo Semiconductors Company Limited (Panasonic Holdings Corporation), Sanyo Electric Company Limited (Panasonic Holdings Corporation)
• Inventors: Ochiai, Isao, Take, Masato
• Granted Patent: US 6,998,701 B2
• Time in Patent Office: Days
• US Class Current: 257/666
• CPC Class Codes: H01L 2224/05554 being square
• CPC Class Codes: H01L 2224/451 with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
• CPC Class Codes: H01L 2224/48247 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/49171 Fan-out arrangements
• CPC Class Codes: H01L 23/295 containing a filler H01L23/296 takes precedence
• CPC Class Codes: H01L 23/3135 Double encapsulation or coating and encapsulation
• CPC Class Codes: H01L 23/49575 Assemblies of semiconductor devices on lead frames
• CPC Class Codes: H01L 24/45 of an individual wire connector
• CPC Class Codes: H01L 24/48 of an individual wire connector
• CPC Class Codes: H01L 24/49 of a plurality of wire connectors
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01019 Potassium [K]
• CPC Class Codes: H01L 2924/01067 Holmium [Ho]
• CPC Class Codes: H01L 2924/01078 Platinum [Pt]
• CPC Class Codes: H01L 2924/10161 with a rectangular active surface
• CPC Class Codes: H01L 2924/1305 Bipolar Junction Transistor [BJT]
• CPC Class Codes: H01L 2924/13091 Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
• CPC Class Codes: H01L 2924/14 Integrated circuits
• CPC Class Codes: H01L 2924/181 : Encapsulation

Abstract

In order to produce no effect even when a first semiconductor chip with a large amount of heat generation and a second semiconductor chip with a small amount of heat generation are integrally sealed by a resin, a resin sealing-type semiconductor device comprises a first semiconductor chip 15 with a large amount of heat generation, whose external electrode leading-out bonding pads 16, 16 . . . are wire-bonded to respective outer leads 25A, 25A . . . and a second semiconductor chip 17 smaller in the amount of heat generation than the first semiconductor chip, whose external electrode leading-out bonding pads 18, 18 . . . are wire-bonded to respective outer leads 25A, 25A . . . , wherein the first semiconductor chip 15 is molded by a high thermal conductive resin 28, and the second semiconductor chip 17 and the first semiconductor chip 15 molded by the high thermal conductive resin are integrally molded by a non-high thermal conductive resin 31.

Claims

1. A resin sealing-type semiconductor device comprising:

a lead frame including a first die pad portion, a second die pad portion, and outer leads provided in a manner corresponding to the respective die pad portions;

a first semiconductor chip with a large amount of heat generation, which is die-bonded to the first die pad portion and whose external electrode leading-out bonding pads and the outer leads corresponding thereto are wire-bonded; and

a second semiconductor chip smaller in the amount of heat generation than the first semiconductor chip, which is die-bonded to the second die pad portion and whose external electrode leading-out bonding pads and the outer leads corresponding thereto are wire-bonded, wherein

the first semiconductor chip is resin-sealed by a high thermal conductive resin, and the second semiconductor chip and the first semiconductor chip resin-sealed by the high thermal conductive resin are integrally resin-sealed by a non-high thermal conductive resin.

2. The resin sealing-type semiconductor device of claim 1, wherein

the first semiconductor chip is of bipolar transistors for electric power, and the second semiconductor chip is an integrated circuit composed of MOS transistors.

3. The resin sealing-type semiconductor device of claim 1, wherein

the non-high thermal conductive resin is composed of a low-stress resin.

4. A manufacturing method of a resin sealing-type semiconductor device comprising:

preparing a lead frame including a first die pad portion, a second die pad portion, and outer leads provided in a manner corresponding to the respective die pad portions;

die-bonding a first semiconductor chip with a large amount of heat generation to the first die pad portion, wire-bonding external electrode leading-out bonding pads of the first semiconductor chip and the outer leads corresponding thereto;

transfer-molding the first semiconductor chip by a high thermal conductive resin;

die-bonding a second semiconductor chip smaller in the amount of heat generation than the first semiconductor chip to the second die pad portion, wire-bonding external electrode leading-out bonding pads of the second semiconductor chip and the outer leads corresponding thereto; and

integrally molding, by a non-high thermal conductive resin, the second semiconductor chip including the first semiconductor chip molded by the high thermal conductive resin.

5. A manufacturing method of a resin sealing-type semiconductor device comprising:

preparing a lead frame including a first die pad portion, a second die pad portion, and outer leads provided in a manner corresponding to the respective die pad portions;

die-bonding a first semiconductor chip with a large amount of heat generation to the first die pad portion, wire-bonding external electrode leading-out bonding pads of the first semiconductor chip and the outer leads corresponding thereto;

molding the first semiconductor chip by potting with a high thermal conductive resin;

die-bonding a second semiconductor chip smaller in the amount of heat generation than the first semiconductor chip to the second die pad portion, wire-bonding external electrode leading-out bonding pads of the second semiconductor chip and the outer leads corresponding thereto; and

integrally molding, by a non-high thermal conductive resin, the second semiconductor chip including the first semiconductor chip molded by the high thermal conductive resin.