Biasing scheme for large format CMOS active pixel sensors

• US 20040201550A1
• Filed: 04/09/2003
• Published: 10/14/2004
• Est. Priority Date: 04/09/2003
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Takayanagi, Isao, Nakamura, Junichi
• Granted Patent: US 7,408,577 B2
• Time in Patent Office: Days
• US Class Current: 345/55
• CPC Class Codes: H04N 25/616 involving a correlated sampling function, e.g. correlated double sampling [CDS] or triple sampling
• CPC Class Codes: H04N 25/65 applied to reset noise, e.g. KTC noise related to CMOS structures by techniques other than CDS
• CPC Class Codes: H04N 25/671 for non-uniformity detection or correction
• CPC Class Codes: H04N 25/677 for reducing the column or line fixed pattern noise
• CPC Class Codes: H04N 25/75 Circuitry for providing, modifying or processing image signals from the pixel array
• CPC Class Codes: H04N 25/77 Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components
• CPC Class Codes: H04N 3/1568 for disturbance correction or prevention within the image-sensor, e.g. biasing, blooming, smearing correction circuits H04N25/62

Abstract

An image sensor includes circuitry compensating for voltage drops in a V_SS line. The image sensor includes a plurality of photoreceptors arranged in a pixel array having a number of column lines, and read-out circuitry on the column lines. The read-out circuitry provides substantially equal currents on each column line so as to compensate for voltage drops in the V_SS line and provide more accurate pixel signals. The image sensor also includes circuitry for filtering noise from a voltage supply line, and for providing hard and/or soft reset operations.

Claims

1. An image sensor comprising:

a pixel array including a plurality of column lines; and

a plurality of read-out circuits respectively coupled to at least some of the plurality of column lines, each of the read-out circuits configured to provide output signals unaffected by unequal bias currents on said plurality of column lines.

2. The image sensor of claim 1, wherein pixels in the array each include a source follower transistor arrangement, and the read-out circuits include a capacitor load for the source follower transistor arrangement.

3. The image sensor of claim 1, further comprising a switch for setting the column lines to ground.

4. The image sensor of claim 1, further comprising a hard reset switch provided in a voltage line to the pixel for hard resetting.

5. The image sensor of claim 4, wherein the hard reset switch comprises an n-MOS transistor operating in a saturation region.

6. The image sensor of claim 4, further comprising a soft reset switch provided in parallel to the hard reset switch.

7. The image sensor of claim 6, wherein the soft reset switch comprises a p-MOS transistor.

8. An image sensor comprising:

a pixel array including a plurality of column lines;

a load transistor connected to at least some of the column lines; and

a circuit applying a substantially equal gate-source voltage to each of the load transistors.

9. A sensor as in claim 8, wherein the circuit comprises a level shift circuit.

10. A sensor as in claim 8, wherein the circuit comprises a clamp circuit.

11. An image sensor comprising:

a pixel array including a plurality of column lines; and

differential amplifier circuitry connected to each of the column lines for maintaining a substantially equal current on each of the plurality of column lines.

12. An image sensor as in claim 11, wherein the differential amplifier circuitry includes a differential amplifier, and a pair of reference voltage inputs to the differential amplifier.

13. An image sensor as in claim 12, further comprising power inputs to the differential amplifier.

14. An image sensor as in claim 13, wherein one of the power inputs is V_AA and the other is V_SS.

15. An image sensor as in claim 14, wherein power input V_AA is different from a V_AA—

_PIX input to the pixel array.

16. An active pixel sensor (APS) comprising:

a plurality of photoreceptors arranged in an array to form a plurality of columns of image sensors, each column of image sensors having circuitry that compensates for voltage drops in at least one of a voltage supply line and a ground line connecting the plurality of columns of image sensors.

17. An APS as in claim 16, wherein each of said plurality of columns of image sensors has readout circuitry that compensates for voltage drops in a V_SS line.

18. An APS as in claim 17, wherein the readout circuitry comprises:

a switchable capacitive load for each of said plurality of columns of image sensors.

19. An APS as in claim 18, wherein the switchable capacitive load comprises:

a parallel arrangement of a signal hold capacitor and a reset hold capacitor.

20. An APS as in claim 19, further comprising a reset switch for connecting each of the hold capacitors to the ground line.

21. An APS as in claim 19, further comprising a signal out line and a reset out line connected between a column line for each column of image sensors and the signal hold capacitor and the reset hold capacitor, respectively.

22. An APS as in claim 17, wherein the readout circuitry includes a load transistor on each column of image sensors, and a level shift circuit supplying a constant gate-source voltage to the load transistor.

23. An APS as in claim 22, wherein the level shift circuit is connected between the V_SS line and the gate of the load transistor.

24. An APS as in claim 17, wherein the readout circuitry includes a load transistor on each column of image sensors, and a clamp circuit supplying a constant gate-source voltage to the load transistor.

25. An APS as in claim 24, wherein the clamp circuit includes a clamp capacitor charged to a clamping voltage during a period when row select pulses are turned off.

26. An APS as in claim 17, wherein the readout circuitry includes a differential amplifier connected between each column of image sensors and the V_SS line.

27. An APS as in claim 26, wherein an output of the differential amplifier connected to the column line.

28. An APS as in claim 16, wherein each column of image sensors as reset circuitry that compensates for voltage drops in a voltage supply line.

29. An APS as in claim 28, wherein the reset circuitry includes a hard reset switch provided in a voltage line to the pixel for hard resetting.

30. An APS as in claim 29, wherein the hard reset switch comprises an n-MOS transistor operating in a saturation region.

31. An APS as in claim 29, further comprising a soft reset switch provided in parallel to the hard reset switch.

32. An APS as in claim 31, wherein the soft reset switch comprises a p-MOS transistor.

34. A method as in claim 29, further comprising the step of

resetting to ground each column of the selected row prior to sampling a signal.

33. A method of operating an image sensor, comprising:

resetting to ground a signal hold capacitor and a reset hold capacitor connected between each column of an image sensor array and ground;

selecting a row to obtain a charge signal from a selected row of photoreceptors;

sampling a signal with a respective signal hold capacitor on each column of the selected row;

resetting each column of the selected row; and

sampling a reset signal with a respective reset hold capacitor on each column of the selected row.

35. A method of operating an image sensor such that pixel signals are compensated for voltage drops in a V_SS line comprising:

charging a clamping capacitor supplying voltage to a gate of a load transistor connected between each column of an image sensor array and ground;

selecting a row to obtain a charge signal from a selected row of photoreceptors; and

sampling a signal on each column of the selected row.

36. A method of operating an image sensor comprising:

supplying a constant current to a gate of a load transistor connected between each column of an image sensor array and ground;

selecting a row to obtain a charge signal from a selected row of photoreceptors; and

sampling a signal on each column of the selected row.

37. A method of forming an active pixel sensor, the method comprising:

forming a plurality of column lines, each of the column lines coupled to a plurality of pixel cells; and

forming readout circuitry on at least some of the plurality of column lines for providing a substantially equal current to each of the plurality of column lines when said pixel cells are read out.

38. A system comprising:

a processor; and

an image sensor integrated circuit comprising;

a pixel array including a plurality of column lines; and

differential amplifier circuitry connected to each of the column lines for maintaining a substantially equal current on each of the plurality of column lines.

39. A method of forming an active pixel sensor, the method comprising:

forming a pixel array having a plurality of column lines; and

forming readout circuitry on at least some of the plurality of column lines for providing output signals unaffected by unequal bias currents on the columns.

40. The method of claim 39, including providing pixels in the array having source follower transistor arrangements, and providing read-out circuits having capacitor loads for the source follower transistor arrangements.