Multiplexer

• US 20040202204A1
• Filed: 04/27/2004
• Published: 10/14/2004
• Est. Priority Date: 05/14/2002
• Status: Abandoned Application

• Current Assignee: ESS Technology Incorporated (Semiconductor Holding Corp.)
• Original Assignee: ESS Technology Incorporated (Semiconductor Holding Corp.)
• Inventors: Cookman, Jordan C., Dong, Ping
• Application Number:
  US10/833,772
• Publication Number:
  US 20040202204A1
• Time in Patent Office: Days
• US Class Current: 370/533
• CPC Class Codes: H01F 2019/085 Transformer for galvanic isolation
• CPC Class Codes: H04L 25/0268 with modulation and subsequent demodulation

Abstract

An electrical isolation barrier for use in a Data Access Arrangement uses a high frequency (HF) transformer 24 to provide isolation. An input signal, which may be analog or digital, is connected to a modulator. The analog output of the modulator is connected to the input of the HF transformer. The output of the HF transformer is connected to the input of a demodulator. Simple amplitude modulation can be used in the modulator to modulate the input signal to the frequency range of operation of the HF transformer. A simple low pass filter may be incorporated in the demodulator to remove harmonic distortion caused by the HF transformer. The output signal of the demodulator is substantially the same as input signal.

Claims

1-39. -39 (cancelled)

40. A multiplexor for use in a data access arrangement, comprising

a first input for receiving a 1-bit digital signal;

a second input for receiving a first number of digital status or control bits;

a framing circuit for combining a second number of framing bits with the first number of digital status or control bits according to a first framing pattern to form a third number of framing output bits, wherein said third number is equal to the sum of the first and second numbers; and

an interleaver which interleaves said third number of framing output bits with a proportional number of bits from the first input, forming a fourth number of multiplexor output bits;

wherein said first framing pattern uniquely indicates the correct framing alignment position of said framing output bits for all combinations of said status or control bits.

41. The multiplexor of claim 40, wherein said first framing pattern prevents the framing output bits from containing a second framing pattern for all possible combinations of said status or control bits, and all possible alignments of said framing output bits.

42. The multiplexor of claim 41, wherein said first framing pattern prevents the framing output bits from containing the logical inverse of said second framing pattern for all possible combinations of said status or control bits, and all possible alignments of said framing output bits.

43. A pair of multiplexors each located on opposite sides of an electrical isolation barrier, each of said multiplexors including

a first input for receiving a 1-bit digital signal;

a second input for receiving a first number of digital status or control bits;

a framing circuit for combining a second number of framing bits with the first number of digital status or control bits according to a first framing pattern to form a third number of framing output bits, wherein said third number is equal to the sum of the first and second numbers; and

an interleaver which interleaves said third number of framing output bits with a proportional number of bits from the first input, forming a fourth number of multiplexor output bits;

wherein the first framing pattern of each multiplexor is equal to the second framing pattern of the other.

44. A multiplexing method providing multiplexor output bits for use in a data access arrangement, comprising

receiving a first 1-bit digital signal;

receiving a first number of digital status or control bits;

providing a second number of framing bits;

providing a first framing pattern;

combining the second number of framing bits with the first number of digital status or control bits according to the first framing pattern to form a third number of framing output bits, wherein said third number is equal to the sum of the first and second numbers; and

interleaving said third number of framing output bits with a proportional number of bits from the first 1-bit digital signal to form a fourth number of multiplexor output bits;

wherein said first framing pattern uniquely indicates the correct framing alignment position of the framing output bits for all combinations of said status or control bits.

45. The method of claim 44, wherein said first framing pattern prevents the framing output bits from containing a second framing pattern for all possible combinations of said status or control bits, and all possible alignments of said framing output bits.

46. The method of claim 45, wherein said first framing pattern prevents the third number of framing output bits from containing the logical inverse of said second framing pattern for all possible combinations of said status or control bits, and all possible alignments of said framing output bits.

47. The method of claim 46, wherein said first framing pattern and said second framing pattern are interchangeable.

48-52. -52 (cancelled)