Method and circuit system for the synchronous transmission of digital signals through a bus description
First Claim
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1. A method for the synchronous transmission of n binary signals through a bus of m leads, where m<
- n, characterized in that it comprises the following operations;
compressing the signals to be transmitted in such a way as to reduce their number and decompressing the signals thus transmitted through the bus until their number is again equal to the number of the signal prior to the encoding.
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Abstract
N binary signals are transmitted through a bus of m leads, where m<n, at the rhythm of a train of clock pulses by encoding a first signal on a second signal. The encoding provides for the information associated with the first signal to be included in the second signal within a predetermined time interval of the clock period preceding each reading clock pulse. In this way one obtains a reduction of the switching activity on the bus and therefore a reduction of the energy consumption.
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21 Claims
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1. A method for the synchronous transmission of n binary signals through a bus of m leads, where m<
- n, characterized in that it comprises the following operations;
compressing the signals to be transmitted in such a way as to reduce their number and decompressing the signals thus transmitted through the bus until their number is again equal to the number of the signal prior to the encoding. - View Dependent Claims (2, 3, 4, 5)
- n, characterized in that it comprises the following operations;
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6. A circuit system for the synchronous transmission on a bus of m leads of n binary signals, where m<
- n, comprising a clock pulse generator, an encoder and a decoder, wherein;
the encoder comprises a multiplicity of input terminals capable of receiving the n signals, including at least a first and a second signal selected for encoding the first signal on the second signal, at least one output terminal connected to a lead of the bus to transmit an encoded signal and first logic means capable of monitoring the first signal and the second signal in order to ascertain whether their state does or does not change between two successive clock pulses, generating the encoded signal in accordance with the following criterion;
when the first signal has not changed in the clock period preceding the reading clock pulse, the encoded signal is equal to the second signal delayed by one clock period,
when the first signal has changed in the clock period preceding the reading clock pulse, the encoded signal is a signal that differs from the second signal by the fact that, in the predetermined time interval of the clock period preceding every reading clock pulse, it is inverted when the second signal has not changed or has changed in the clock period preceding the reading clock pulse, otherwise, when the second signal has changed in the clock period preceding the reading clock pulse, in the same predetermined time interval it remains equal to the second signal, andthe decoder comprises at least one input terminal connected to a lead of the bus to receive an encoded signal, a multiplicity of output terminals, including at least two terminals for two output signals corresponding to the first and the second signal selected for encoding and logic means capable of reading the encoded signal arriving from the lead of the transmission bus on the reading edge of clock pulse following the clock pulse during which the encoding was effected and sending it as first output signal to a first output terminal, monitoring the encoded signal to ascertain whether its state has or has not changed during the predetermined time interval and reconstructing the first signal as second output signal at a second output terminal, inverting or not inverting the second output signal in the clock period preceding the reading clock pulse in accordance with the state ascertained by the previous operation.
- n, comprising a clock pulse generator, an encoder and a decoder, wherein;
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7. A method for encoding a first digital signal onto a second digital signal, comprising:
generating an output signal having a state at a given clock signal edge which matches a state of the second digital signal and having a transition or not in state occurring in a time period preceding the given clock signal edge that is indicative of a state of the first digital signal. - View Dependent Claims (8, 9, 10, 11)
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12. A method for decoding an encoded digital signal, comprising:
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generating a first output signal having a state at a given clock signal edge which matches a state of the encoded digital signal; and
generating a second output signal having a state having a state that is indicated by a transition or not in state of the encoded digital signal which occurs in a time period preceding the given clock signal edge. - View Dependent Claims (13, 14)
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15. An encoder for encoding a first digital signal onto a second digital signal, comprising:
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a first circuit that controls a state of an output digital to match a state of the second digital signal at a given clock signal edge; and
a second circuit that controls the state of the output digital signal to transition or not during a time period preceding the given clock signal edge in a manner which is indicative of a state of the first digital signal . - View Dependent Claims (16, 17, 18)
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19. A decoder for decoding an encoded digital signal, comprising:
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a first circuit that generates a first output signal having a state at a given clock signal edge which matches a state of the encoded digital signal; and
a second circuit that generates a second output signal having a state having a state that is indicated by a transition or not in state of the encoded digital signal which occurs in a time period preceding the given clock signal edge. - View Dependent Claims (20, 21)
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Specification