METHODS TO FORM METAL LINES USING SELECTIVE ELECTROCHEMICAL DEPOSITION

• US 20040203181A1
• Filed: 04/11/2003
• Published: 10/14/2004
• Est. Priority Date: 04/11/2003
• Status: Active Grant

• Current Assignee: Applied Materials Incorporated
• Original Assignee: Applied Materials Incorporated
• Inventors: Bachrach, Robert Z., Shang, Quanyuan, White, John M., Law, Kam S.
• Granted Patent: US 6,887,776 B2
• Time in Patent Office: Days
• US Class Current: 438/30
• CPC Class Codes: H01L 29/42384 for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor
• CPC Class Codes: H01L 29/4908 for thin film semiconductor, e.g. gate of TFT
• CPC Class Codes: H01L 29/66757 Lateral single gate single channel transistors with non-inverted structure, i.e. the channel layer is formed before the gate
• CPC Class Codes: H01L 29/66765 Lateral single gate single channel transistors with inverted structure, i.e. the channel layer is formed after the gate
• CPC Class Codes: H01L 29/78696 characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621

Abstract

Methods are provided for forming a transistor for use in an active matrix liquid crystal display (AMLCD). In one aspect a method is provided for processing a substrate including providing a glass substrate, depositing a conductive seed layer on a surface of the glass substrate, depositing a resist material on the conductive seed layer, patterning the resist layer to expose portions of the conductive seed layer, and depositing a metal layer on the exposed portions of the conductive seed layer by an electrochemical technique.

Claims

1. A method of forming a transistor for use in an active matrix liquid crystal display (AMLCD), comprising:

providing a glass substrate; and

forming a metal gate on the glass substrate by a technique comprising;

depositing a conductive seed layer on a surface of the glass substrate;

depositing a resist material on the conductive seed layer;

patterning the resist layer to expose portions of the conductive seed layer; and

depositing a metal layer on the exposed portions of the conductive seed layer by an electrochemical deposition technique.

2. The method of claim 1, further comprising removing the resist material.

3. The method of claim 2, further comprising etching the exposed portions of the conductive seed layer.

4. The method of claim 3, further comprising:

depositing one or more dielectric layers on the metal layer; and

forming one or more source regions and one or more drain regions on the one or more dielectric layers.

5. The method of claim 1, wherein the electrochemical deposition technique comprises electroplating or electroless deposition.

6. The method of claim 1, wherein the seed layer comprises a metal selected from the group consisting of copper, nickel, tungsten, molybdenum, cobalt, ruthenium, titanium, zirconium, hafnium, niobium, tantalum, vanadium, chromium, manganese, iron, palladium, platinum, aluminum, and combinations thereof.

7. The method of claim 1, wherein the glass substrate comprises a material selected from the group consisting of undoped silica glass (USG), phosphorus doped glass (PSG), boron-phosphorus doped glass (BPSG), soda-lime glass, borosilicate glass, sodium borosilicate glass, alkali-metal borosilicate, aluminosilicate glass, aluminoborosilicate glass, alkaline earth aluminoborosilicate glass, alkaline earth-metal aluminoborosilicate glass, and combinations thereof.

8. The method of claim 1, further comprising depositing a barrier layer on a surface of the glass substrate prior to deposition of the seed layer.

9. The method of claim 1, wherein the seed layer is deposited by a process selected from the group of thermal chemical vapor deposition, plasma chemical vapor deposition, atomic layer deposition, evaporation, and combinations thereof.

10. A method of forming a transistor for use in an active matrix liquid crystal display (AMLCD), comprising:

providing a glass substrate;

depositing a conductive seed layer on a surface of the glass substrate;

depositing a resist material on the conductive seed layer;

patterning the resist layer to expose the conductive seed layer;

etching exposed portions of the conductive seed layer;

removing the resist material; and

depositing a metal layer on remaining portions of the conductive seed layer by an electrochemical deposition technique.

11. The method of claim 10, further comprising depositing a dielectric layer on the metal layer.

12. The method of claim 10, wherein the electrochemical deposition technique comprises electroplating or electroless deposition.

13. The method of claim 10, wherein the seed layer comprises a metal selected from the group consisting of copper, nickel, tungsten, molybdenum, cobalt, ruthenium, titanium, zirconium, hafnium, niobium, tantalum, vanadium, chromium, manganese, iron, palladium, platinum, aluminum, and combinations thereof.

14. The method of claim 10, wherein the glass substrate comprises a material selected from the group consisting of undoped silica glass (USG), phosphorus doped glass (PSG), boron-phosphorus doped glass (BPSG), soda-lime glass, borosilicate glass, sodium borosilicate glass, alkali-metal borosilicate, aluminosilicate glass, aluminoborosilicate glass, alkaline earth aluminoborosilicate glass, alkaline earth-metal aluminoborosilicate glass, and combinations thereof.

15. The method of claim 10, further comprising depositing a barrier layer on a surface of the glass substrate prior to deposition of the seed layer.

16. The method of claim 10, wherein the seed layer is deposited by a process selected from the group of thermal chemical vapor deposition, plasma chemical vapor deposition, atomic layer deposition, evaporation, and combinations thereof.

17. A method of forming a transistor for use in an active matrix liquid crystal display (AMLCD), comprising:

providing a glass substrate;

forming one or more doped semiconductor layers having source regions and drain regions formed therein;

forming one or more gate dielectric layers on the one or more doped semiconductor layers;

forming one or more metal gates on the one or more gate dielectric layers by;

depositing a conductive seed layer on one or more gate dielectric layers;

depositing a resist material on the conductive seed layer;

patterning the resist layer to expose portions of the conductive seed layer;

depositing a metal layer on the exposed portions of the conductive seed layer by an electrochemical technique; and

removing the resist material;

depositing an interlayer dielectric material on the substrate and over the one or more metal gates;

patterning one or more gate dielectric layers and the interlayer dielectric material to form feature definitions exposing underlying source regions and drain regions; and

depositing a metal layer in the feature definitions to form a contact.

18. The method of claim 17, further comprising depositing a dielectric layer on the glass substrate prior to forming a doped semiconductor layer.

21. The method of claim 17, further comprising etching exposed conductive seed layer material.

22. The method of claim 17, wherein the electrochemical deposition technique comprises electroplating or electroless deposition.

19-20. -20. (Cancelled)

23. A method of forming a transistor for use in an active matrix liquid crystal display (AMLCD), comprising:

providing a glass substrate;

forming one or more doped semiconductor layers having source regions and drain regions formed therein;

forming one or more gate dielectric layers on the one or more doped semiconductor layers;

forming one or more metal gates on the one or more gate dielectric layers by;

depositing a conductive seed layer on the one or more gate dielectric layers;

depositing a resist material on the conductive seed layer;

patterning the resist layer to expose the conductive seed layer;

etching exposed portions of the conductive seed layer;

removing the resist material; and

depositing a metal layer on remaining portions of the conducive seed layer by an electrochemical techniques;

depositing an interlayer dielectric material on the substrate and over the one or more metal gates;

patterning one or more gate dielectric layers and the interlayer dielectric material to form feature definitions exposing underlying source regions and drain regions; and

depositing a metal layer in the feature definitions to form a contact.

24. The method of claim 23, wherein the electrochemical deposition technique comprises electroplating or electroless deposition.