Trench semiconductor device having gate oxide layer with mulitiple thicknesses and processes of fabricating the same

• US 20040203200A1
• Filed: 03/04/2004
• Published: 10/14/2004
• Est. Priority Date: 05/25/1999
• Status: Active Grant

• Current Assignee: Advanced Analogic Technologies Incorporated (Skyworks Solutions Incorporated)
• Original Assignee: Advanced Analogic Technologies Incorporated (Skyworks Solutions Incorporated)
• Inventors: Williams, Richard K., Grabowski, Wayne B.
• Granted Patent: US 6,900,100 B2
• Time in Patent Office: Days
• US Class Current: 438/202
• CPC Class Codes: H01L 29/0847 of field-effect transistors with insulated gate H01L29/0653 takes precedence; with a passive supplementary region between source or drain and substrate related to punch-through, capacity or isolation phenomena H01L29/1079; with LDD or DDD structure H01L29/7833; for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/0878 Impurity concentration or distribution
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/4232 with insulated gate
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/4238 characterised by the surface lay-out
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7397 and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
• CPC Class Codes: H01L 29/7808 the other device being a breakdown diode, e.g. Zener diode
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 29/7828 without inversion channel, e.g. vertical ACCUFETs, normally-on vertical MISFETs
• CPC Class Codes: H01L 29/8083 Vertical transistors SIT H01L29/7722

Abstract

The a trench semiconductor device such as a power MOSFET the high electric field at the corner of the trench is diminished by increasing the thickness of the gate oxide layer at the bottom of the trench. Several processes for manufacturing such devices are described. In one group of processes a directional deposition of silicon oxide is performed after the trench has been etched, yielding a thick oxide layer at the bottom of the trench. Any oxide which deposits on the walls of the trench is removed before a thin gate oxide layer is grown on the walls. The trench is then filled with polysilicon in or more stages. In a variation of the process a small amount of photoresist is deposited on the oxide at the bottom of the trench before the walls of the trench are etched. Alternatively, polysilicon can be deposited in the trench and etched back until only a portion remains at the bottom of the trench. The polysilicon is then oxidized and the trench is refilled with polysilicon. The processes can be combined, with a directional deposition of oxide being followed by a filling and oxidation of polysilicon. A process of forming a “keyhole” shaped gate electrode includes depositing polysilicon at the bottom of the trench, oxidizing the top surface of the polysilicon, etching the oxidized polysilicon, and filling the trench with polysilicon.

Claims

1. A process of fabricating a trench semiconductor device comprising:

providing a semiconductor material;

depositing a hard mask layer over a surface of said semiconductor material;

forming an opening in said hard mask layer;

etching said semiconductor through said opening in said hard mask layer to form a trench extending from said surface into said semiconductor material, said trench being bounded on one side by a mesa;

directionally depositing a thick oxide layer on said semiconductor material, said oxide layer depositing preferentially on horizontal surfaces so as to form a first thick portion in a bottom of said trench and a second thick portion on said hard mask layer, and a thin portion on said sidewall of said trench;

removing said thin portion of said thick oxide layer from said sidewall of said trench;

growing a gate oxide layer on said sidewall of said trench

forming a polysilicon layer in said trench, said polysilicon layer having a surface abutting said hard mask layer; and

removing said second thick portion of said thick oxide layer from said hard mask layer, said mesa being protected by said hard mask layer.

2. The process of claim 1 wherein said hard mask layer comprises silicon nitride.

3. The process of claim 1 wherein forming a polysilicon layer in said trench comprises depositing a thick polysilicon layer in said trench and over second thick portion of said thick oxide layer and etching said thick polysilicon layer back until a surface of said thick polysilicon layer is adjacent said hard mask layer.

4. The process of claim 1 comprising annealing said polysilicon layer after the removal of said second thick portion of said thick oxide layer but before the removal of said hard mask layer to form a thick oxide cap over said polysilicon layer.

5. The process of claim 1 comprising forming a thin oxide layer under said hard mask layer and removing said thin oxide layer from said mesa after removing said hard mask layer, the removal of said thin oxide layer from said mesa exposing said silicon material.

6. A process of fabricating a trench semiconductor device comprising:

providing a semiconductor material;

forming an oxide layer on a surface of said semiconductor material;

depositing a hard mask layer on said oxide layer;

forming an opening in said hard mask layer said oxide layer; and

etching said semiconductor through said opening to form a trench extending from said surface into said semiconductor material.

7. The process of claim 6 wherein said hard mask layer comprises silicon nitride.

8. A process of fabricating a trench semiconductor device comprising:

providing a semiconductor material;

forming a trench in said semiconductor material, said trench extending from a surface of said semiconductor material into said semiconductor material;

depositing a polysilicon layer, said polysilicon layer filling said trench and overflowing said surface of said semiconductor material; and

removing a sufficient amount of said polysilicon layer such that a surface of said polysilicon layer is substantially coplanar with said surface of said semiconductor material, said removing comprising chemical-mechanical polishing.

9. The process of claim 8 comprising performing the following after forming said trench but before depositing said polysilicon layer:

directionally depositing a thick oxide layer on said semiconductor material, said thick oxide layer depositing preferentially on horizontal surfaces so as to form a first thick portion in a bottom of said trench and a thin portion on a sidewall of said trench.

10. The process of claim 9 comprising:

forming a second oxide layer over said surfaces of said polysilicon layer and said semiconductor material;

forming a mask layer over said second oxide layer;

etching said second oxide layer through an opening in said mask layer so as to leave a portion of said second oxide layer overlying said surface of said polysilicon layer and a portion of said surface of said semiconductor material.

11. The process of claim 9 comprising the following after removing a sufficient amount of said polysilicon layer:

annealing said polysilicon layer to form an oxide cap.

12. A process of fabricating a trench semiconductor device comprising:

providing a semiconductor material;

forming a trench in said semiconductor material, said trench extending from a surface of said semiconductor material into said semiconductor material;

thermally growing an oxide lining on the sidewalls and bottom of said trench;

directionally depositing a thick oxide layer, said oxide layer depositing preferentially on horizontal surfaces so as to form a first thick portion over said oxide lining at a bottom of said trench and a thin portion on said oxide lining on said sidewall of said trench.

13. The process of claim 12 comprising thermally growing and removing a sacrificial oxide layer on the sidewalls of said trench before thermally growing said oxide lining.

14. A process of fabricating a trench semiconductor device comprising:

providing a semiconductor material;

forming a trench in said semiconductor material, said trench extending from a surface of said semiconductor material into said semiconductor material;

directionally depositing a thick oxide layer on said semiconductor material, said oxide layer depositing preferentially on horizontal surfaces so as to form a first thick portion in a bottom of said trench and a second thick portion over said surface of said semiconductor material, and a thin portion on a sidewall of said trench;

removing said thin portion of said thick oxide layer from said sidewall of said trench;

growing a gate oxide layer on said sidewall of said trench

depositing a first polysilicon layer, said first polysilicon layer filling said trench and overflowing said second thick portion of said thick oxide layer;

etching a sufficient amount of said first polysilicon layer such that a surface of said polysilicon layer is located inside said trench;

depositing a second polysilicon layer; and

etching a sufficient amount of said second polysilicon layer such that a surface of said second polysilicon layer is located adjacent said second thick portion of said thick oxide layer.

15. A process of fabricating a trench semiconductor device comprising:

providing a semiconductor material;

forming a trench in said semiconductor material, said trench extending from a surface of said semiconductor material into said semiconductor material;

directionally depositing a thick oxide layer on said semiconductor material, said oxide layer depositing preferentially on horizontal surfaces so as to form a thick portion in a bottom of said trench and a thin portion on a sidewall of said trench;

depositing a photoresist layer;

removing all of said photoresist layer except for a remaining portion of said photoresist layer that overlies said thick portion of said thick oxide layer; and

removing said thin portion of said thick oxide layer from said sidewall of said trench.

16. The process of claim 15 comprising removing said remaining portion of said photoresist layer.

17. The process of claim 16 comprising growing a gate oxide layer on said sidewall of said trench.

18. The process of claim 17 comprising forming a polysilicon layer in said trench.

19. A process of fabricating a trench semiconductor device comprising:

providing a semiconductor material;

forming a trench in said semiconductor material, said trench extending from a surface of said semiconductor material into said semiconductor material;

directionally depositing a thick oxide layer on said semiconductor material, said oxide layer depositing preferentially on horizontal surfaces so as to form a thick portion in a bottom of said trench and a thin portion on a sidewall of said trench;

depositing a polysilicon layer;

removing all of said polysilicon layer except for a remaining portion of said polysilicon layer that overlies said thick portion of said thick oxide layer;

oxidizing said remaining portion of said polysilicon layer; and

removing said thin portion of said thick oxide layer from said sidewall of said trench.

20. The process of claim 19 wherein oxidizing said remaining portion of said polysilicon layer comprises heating said remaining portion of said polysilicon layer to a temperature in the range of 700 to 950°

C.

21. A process of fabricating a trench semiconductor device comprising:

providing a semiconductor material;

depositing a first hard mask layer over a surface of said semiconductor material;

forming an opening in said first hard mask layer;

etching said semiconductor through said opening in said first hard mask layer to form a trench extending from said surface into said semiconductor material, said trench being bounded on one side by a mesa;

directionally depositing a thick oxide layer on said semiconductor material, said oxide layer depositing preferentially on horizontal surfaces so as to form a first thick portion in a bottom of said trench and a second thick portion on said first hard mask layer, and a thin portion on said sidewall of said trench;

removing said thin portion of said thick oxide layer from said sidewall of said trench;

growing a gate oxide layer on said sidewall of said trench

depositing a first polysilicon layer;

etching a sufficient amount of said first polysilicon layer such that a surface of said first polysilicon layer is located adjacent said first hard mask layer; and

depositing a second polysilicon layer atop said first polysilicon layer and said hard mask.

22. The process of claim 21 comprising depositing a second hard mask layer over said second polysilicon layer.

23. The process of claim 22 wherein said second hard mask layer comprises silicon nitride or polyimide.

24. The process of claim 23 comprising removing said second hard mask layer and said second polysilicon layer from an active area of said semiconductor device, leaving remaining portions of said second hard mask layer and said second polysilicon layer in a gate bus area of said device.

25. The process of claim 24 comprising heating said device to form an oxide cap on said first polysilicon layer in said trench and an oxide layer on an exposed edge of said remaining portion of second polysilicon layer.

26. The process of claim 25 comprising removing said remaining portion of said hard mask layer from said gate bus area.

27. A process of fabricating a trench semiconductor device comprising:

providing a semiconductor material;

forming a mask layer on a surface of said semiconductor material;

forming a first opening in said mask layer, said first opening exposing an exposed are of said surface of said semiconductor material;

depositing a second layer on said mask layer and on said exposed area;

anisotropically etching said second layer so as to leave sidewall spacers on edges of said mask layer facing said first opening, the separation between said sidewall spacers forming a second opening narrower than said first opening;

forming a trench in said semiconductor material by etching said semiconductor material through said second opening;

forming a gate oxide layer on a sidewall of said trench;

directionally depositing a thick oxide layer, said thick oxide layer depositing preferentially on horizontal surfaces so as to form a first thick portion in a bottom of said trench and a second thick portion on said second layer; and

forming a polysilicon gate in said trench.

28. The process of claim 27 wherein forming a polysilicon gate comprises:

depositing a polysilicon layer in said trench and over a surface of said second thick portion of said oxide layer; and

etching said polysilicon layer until a surface of said polysilicon layer is adjacent said sidewall spacers.

29. The process of claim 28 comprising removing said second thick portion of said thick oxide layer.

30. The process of claim 27 wherein forming a mask layer comprises:

forming a first oxide sublayer on said surface of said semiconductor material;

depositing a nitride sublayer on said first oxide sublayer; and

depositing a second oxide sublayer on said nitride sublayer.

31. The process of claim 30 comprising removing said second oxide sublayer before forming said trench, leaving said sidewall spacer on edges of said first oxide sublayer and said nitride sublayer.

32. A process of fabricating a trench semiconductor device comprising:

providing a semiconductor material;

forming a mask layer on a surface of said semiconductor material;

forming a opening in said mask layer;

forming a trench in said semiconductor material by etching said semiconductor material through said opening;

forming an oxide lining on a bottom and sidewalls of said trench;

depositing a first polysilicon layer in said trench;

etching said first polysilicon layer such that a remaining portion of said first polysilicon layer remains over said oxide lining at the bottom of said trench;

removing said oxide lining except for a remaining portion of said oxide lining that is adjacent said remaining portion of said first polysilicon layer;

anisotropically etching a top surface of said remaining portion of said first polysilicon layer so as to depress said top surface to a level below a top surface of said remaining portion of said oxide lining;

heating said device so as to form a first oxide layer on said top surface of said first polysilicon layer and a second oxide layer on exposed portions of said sidewalls of said trench;

removing said first oxide layer while leaving a portion of said second oxide layer on the sidewalls of said trench; and

depositing a second polysilicon layer in said trench.

33. The process of claim 32 wherein said second polysilicon layer extends over said surface of said semiconductor material, said process comprising etching said second polysilicon layer such that a surface of said second polysilicon layer is substantially coplanar with said surface of said semiconductor material.

34. A process of fabricating a trench semiconductor device comprising:

providing a semiconductor material;

forming a mask layer on a surface of said semiconductor material;

forming a opening in said mask layer;

forming a trench in said semiconductor material by etching said semiconductor material through said opening;

forming an oxide lining on a bottom and sidewalls of said trench;

depositing a photoresist layer in said trench;

washing said photoresist layer such that a remaining portion of said photoresist layer remains over said oxide lining at the bottom of said trench;

removing said oxide lining except for a remaining portion of said oxide lining that is adjacent said remaining portion of said photoresist layer, thereby leaving exposed portions of said sidewalls of said trench;

removing said remaining portion of said photoresist layer;

growing a gate oxide layer on said exposed portions of said sidewalls of said trench; and

depositing a polysilicon layer in said trench.