Interface transceiver power management method and apparatus including controlled circuit complexity and power supply voltage

• US 20040203477A1
• Filed: 11/21/2002
• Published: 10/14/2004
• Est. Priority Date: 11/21/2002
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Carballo, Juan-Antonio, Burns, Jeffrey L.
• Granted Patent: US 8,271,055 B2
• Time in Patent Office: Days
• US Class Current: 455/69
• CPC Class Codes: H04W 52/04 TPC

Abstract

An interface transceiver power management method and apparatus including controlled circuit complexity and power supply voltage reduces power consumption when interface conditions will support a transceiver having reduced complexity. The power supply voltage of the reduced complexity logic is then reduced if the lowered complexity will support a lower power supply voltage. The reduced complexity in combination with a reduced power supply voltage decreases power consumption to a greater degree than reducing transceiver complexity alone.

The complexity of processing blocks within the receiver and/or transmitter are adjusted in conformity with one or more selection signals and an operating voltage level is selected in accordance with the requirements of the reduced complexity circuit. An interface quality measurement circuit may provide the selection signal, so that the transceiver complexity is adjusted in response to measured interface conditions or an external pin or register bit may be coupled to a select input.

Claims

15. A transceiver for linking electronic devices, comprising:

at least one interface circuit including an internal processing block, said interface circuit coupled to one or more interface signals;

means for selecting a complexity and operating voltage level of said interface circuit, whereby power consumption of said interface circuit is reduced when channel conditions permit.

16. The transceiver of claim 15, wherein said selecting means comprises:

complexity selection means for disabling a portion of said interface circuit; and

power supply means for providing a lowered power supply voltage to a remainder of said interface circuit when said portion of said interface circuit is disabled.

17. The transceiver circuit of claim 15, wherein said selecting means sets a body voltage bias level of at least one transistor within said interface circuit.

22. The method of claim 17, wherein said power supply selecting selects a bias voltage of a body terminal of at least one transistor within said processing block.

18. A method of controlling power consumption in an interface transceiver, comprising:

receiving an indication of that power consumption of said interface transceiver may be reduced;

in response to said receiving, selecting a complexity of said receiver; and

in further response to said receiving, selecting a power supply voltage level of at least one internal processing block of said interface transceiver.

1. A transceiver for linking electronic devices, comprising:

at least one interface circuit including an internal processing block having selectable complexity, said interface circuit coupled to one or more interface signals;

a power supply circuit coupled to said internal processing block and having a selectable output voltage level; and

a select input coupled to said at least one interface circuit for receiving a selection signal, whereby a level of complexity of said processing block is selected by a logic state of said select input and wherein a power supply voltage level of said power supply circuit is further selected in conformity with said select input.

2. The interface transceiver of claim 1, wherein said at least one interface circuit comprises a transmitter circuit, and wherein said power supply circuit supplies a selectable voltage level to a power supply of at least one signal processing block within said transmitter circuit.

3. The interface transceiver of claim 1, wherein said at least one interface circuit comprises a receiver circuit, and wherein said power supply circuit supplies a selectable voltage level to a power supply of at least one signal processing block within said receiver circuit.

4. The interface transceiver of claim 1, further comprising an interface quality measurement circuit, and wherein said select input is coupled to an output of said interface quality measurement circuit.

5. The interface transceiver of claim 4, wherein said power supply circuit is further coupled to said interface quality measurement circuit for selecting said output voltage level.

6. The interface transceiver of claim 4, further comprising a communication link for transmitting an output of said quality measurement circuit to a remote transceiver over said one or more interface signals.

7. The interface transceiver of claim 1, further comprising a communication link for transmitting a state of said select input to a remote transceiver over said one or more interface signals.

8. The interface transceiver of claim 1, wherein said at least one interface circuit includes a plurality of alternate circuit blocks, wherein a first one of said circuit blocks is disabled in response to said logic state of said select input, and wherein a second one of said alternate circuit blocks is enabled in response to said logic state of said select input, and wherein said power supply circuit supplies a first voltage level to said first one of said circuit blocks and a second voltage level to a second one of said circuit blocks.

9. The interface transmitter of claim 8, wherein said power supply circuit supplies power to only an enabled one of said first circuit block and said second circuit block.

10. The interface transceiver of claim 1, wherein said select input is coupled to said power supply control circuit for controlling a power supply input of said at least one interface circuit, whereby said at least one interface circuit is disabled by removing power in response to said logic state of said select input.

11. The interface transceiver of claim 1, wherein said power supply circuit includes two or more power supply outputs and a switching circuit for selecting between a first one of said power supply outputs and a second one of said power supply outputs in conformity with said selected level of complexity.

12. The interface transceiver of claim 1, wherein said power supply circuit is a programmable power supply circuit having a settable output voltage, and wherein said output voltage is set in conformity with said selected level of complexity.

13. The interface transceiver of claim 1, wherein said power supply circuit has an output coupled to the body terminal of at least one transistor within said processing block, whereby a threshold voltage of said at least one transistor is selected in conformity with said selected complexity.

14. The interface transceiver of claim 13, wherein said power supply circuit has two bias outputs each coupled to a body terminal of an associated transistor of at least one complementary transistor pair within said processing block, whereby a threshold voltage of each transistor of said complementary transistor pair is selected in conformity with said selected complexity.

19. The method of claim 18, further comprising:

measuring a quality of an interface signal coupled to said interface transceiver;

determining whether or not said quality is above a threshold level; and

in response to determining that said quality is above a threshold level, generating said indication.

20. The method of claim 19, further comprising communicating a state of said indication to a remote transceiver.

21. The method of claim 18, wherein said power supply selecting is made in response to said selecting of said complexity.

21-1. The method of claim 18, wherein said selecting of complexity is made in response to said power supply selecting.