Interface transceiver power mangagement method and apparatus

• US 20040203483A1
• Filed: 11/07/2002
• Published: 10/14/2004
• Est. Priority Date: 11/07/2002
• Status: Abandoned Application

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Carballo, Juan-Antonio, Boerstler, David William, Burns, Jeffrey L.
• Application Number:
  US10/289,777
• Publication Number:
  US 20040203483A1
• Time in Patent Office: Days
• US Class Current: 455/88
• CPC Class Codes: H04B 1/16 Circuits

Abstract

An interlace transceiver power management method and apparatus reduces power consumption when interface conditions will support a transceiver having reduced complexity. Characteristics of the receiver and/or transmitter are adjusted in conformity with one or more selection signals. An interface quality measurement circuit may provide the selection signal, so that the transceiver complexity is adjusted in response to measured interface conditions or an external pin or register bit may be coupled to a select input. The receiver complexity adjustment may include the receiver sampling depth, window width, resolution or equalization complexity or other characteristic having an impact on receiver circuit power consumption. The transmitter complexity may be equalization, transmitter power or other characteristic having an impact on transmitter circuit power consumption. The select signal may be communicated from one transceiver to another, so that the power consumption at a remote location is determined by local measurement or programming.

Claims

1. A transceiver for interconnecting electronic devices, comprising:

at least one interface circuit having selectable power consumption coupled to one or more interface signals;

a select input coupled to said at least one interface circuit for receiving a selection signal, whereby a level of complexity of said one or more interface circuits is selected by a logic state of said select input.

2. The interface transceiver of claim 1, wherein said at least one interface circuit comprises a transmitter circuit.

3. The interface transceiver of claim 2, wherein said transmitter circuit comprises an digital equalization filter coupled to said select input and having a selectable number of multiple taps, and wherein said number of said multiple taps is selected in conformity with said logic state of said select input.

4. The interface transceiver of claim 2, wherein said transmitter circuit has variable power output, and wherein a level of said variable power output is selected in conformity with said logic state of said select input.

5. The interface transceiver of claim 1, wherein said at least one interface circuit comprises a receiver circuit.

6. The interface transceiver of claim 5, wherein said receiver circuit comprises an digital equalization filter having multiple taps and coupled to said select input, and wherein said number of said multiple taps is selected in conformity with said logic state of said select input.

7. The interface transceiver of claim 5, wherein said receiver circuit comprises a phase control circuit having a selectable resolution and coupled to said select input, and wherein said selectable resolution is selected in conformity with said logic state of said select input.

8. The interface transceiver of claim 5, wherein said receiver circuit comprises a sample memory for processing said one or more interface signals and coupled to said select input, said sample memory having a selectable active size, and wherein said selectable active size is selected in conformity with said logic state of said select input.

9. The interface transceiver of claim 5, wherein said receiver circuit comprises a signal processing block having a selectable sampling window for processing bits received from one of said interface signals and coupled to said select input, and wherein said selectable sampling window is selected in conformity with said logic state of said select input.

10. The interface transceiver of claim 5, wherein said receiver circuit comprises an error-correction circuit having a selectable correction depth and coupled to said select input, and wherein said selectable correction depth is selected in conformity with said logic state of said select input.

11. The interface transceiver of claim 1, further comprising an interface quality measurement circuit, and wherein said select input is coupled to an output of said interface quality measurement circuit.

12. The interface transceiver of claim 11, further comprising a communication link for transmitting an output of said quality measurement circuit to a remote transceiver over said one or more interface signals.

13. The interface transceiver of claim 11, wherein said at least one interface circuit comprises a transmitter circuit, wherein said transmitter circuit comprises an digital equalization filter coupled to said select input and having a selectable number of multiple taps, and wherein said number of said multiple taps is selected in conformity with said logic state of said select input.

14. The interface transceiver of claim 11, wherein said at least one interface circuit comprises a transmitter circuit, wherein said transmitter circuit has variable power output, and wherein a level of said variable power output is selected in conformity with said logic state of said select input.

15. The interface transceiver of claim 11, wherein said at least one interface circuit comprises a receiver circuit, wherein said receiver circuit comprises an digital equalization filter having multiple taps and coupled to said select input, and wherein said number of said multiple taps is selected in conformity with said logic state of said select input.

16. The interface transceiver of claim 11, wherein said at least one interface circuit comprises a receiver circuit, wherein said receiver circuit comprises a phase control circuit having a selectable resolution and coupled to said select input, and wherein said selectable resolution is selected in conformity with said logic state of said select input.

17. The interface transceiver of claim 11, wherein said at least one interface circuit comprises a receiver circuit, wherein said receiver circuit comprises a sample memory for processing said one or more interface signals and coupled to said select input, said sample memory having a selectable active size, and wherein said selectable active size is selected in conformity with said logic state of said select input.

18. The interface transceiver of claim 11, wherein said at least one interface circuit comprises a receiver circuit, wherein said receiver circuit comprises a signal processing block having a selectable sampling window for processing bits received from one of said interface signals and coupled to said select input, and wherein said selectable sampling window is selected in conformity with said logic state of said select input.

19. The interface transceiver of claim 1, further comprising a communication link for transmitting a state of said select input to a remote transceiver over said one or more interface signals.

20. The interface transceiver of claim 1, wherein said at least one interface circuit includes a plurality of alternate circuit blocks, wherein a first one of said circuit blocks is disabled in response to said logic state of said select input, and wherein a second one of said alternate circuit blocks is enabled in response to said logic state of said select input.

21. The interface transceiver of claim 1, wherein said at least one interface circuit includes a state machine, wherein a complexity of said state machine is adjusted in conformity with said logic state of said select input.

22. The interface transceiver of claim 1, wherein said select input is coupled to a clock disable circuit within said at least one interface circuit, whereby said at least one interface circuit blocks is disabled by disabling a clock input to said at least one interface circuit.

23. The interface transceiver of claim 1, wherein said select input is coupled to a reset input of said at least one interface circuit, whereby said at least one interface circuit is disabled by holding said at least one interface circuit in a reset condition in response to said logic state of said select input.

24. The interface transceiver of claim 1, wherein said select input is coupled to a power supply control circuit for controlling a power supply input of said at least one interface circuit, whereby said at least one interface circuit is disabled by removing power in response to said logic state of said select input.

25. A method of controlling power consumption in an interface transceiver, comprising:

receiving an indication of that power consumption of said interface transceiver may be reduced; and

in response to said receiving, selecting a complexity of said receiver.

26. The method of claim 25, further comprising:

measuring a quality of an interface signal coupled to said interface transceiver;

determining whether or not said quality is above a threshold level; and

in response to determining that said quality is above a threshold level, generating said indication.

27. The method of claim 25, further comprising communicating a state of said indication to a remote transceiver.