Method and apparatus for use in securing an electronic device such as a cell phone

• US 20040204003A1
• Filed: 07/31/2002
• Published: 10/14/2004
• Est. Priority Date: 05/08/2002
• Status: Active Grant

• Current Assignee: Daoling Technologies Inc. (Wi-LAN Inc.)
• Original Assignee: MediaTek, Inc.
• Inventors: Soerensen, Joern, Birk, Palle, Boutaud, Frederic
• Granted Patent: US 7,454,169 B2
• Time in Patent Office: Days
• US Class Current: 455/550.1
• CPC Class Codes: G06F 21/73 by creating or determining hardware identification, e.g. serial numbers
• CPC Class Codes: H04W 12/126 Anti-theft arrangements, e.g. protection against subscriber identity module [SIM] cloning
• CPC Class Codes: H04W 88/02 Terminal devices

Abstract

The present invention is directed to methods and apparatus which may be used to help prevent electronic devices such as, for example, cell phones from operating with software copied from (and only authorized for use by) another device. The present invention is also directed to devices such as, for example, cell phones, that employ any of such methods and apparatus.

Aspects of the present invention compare a program identifier (associated with software stored in a device) to a reference identifier for the device so as to determine whether the software is authorized for use with that device. Some embodiments respond to the comparison substantially in hardware, so that the software being checked is less able to prevent the device from being disabled in the event that the program identifier and the reference identifier do not match one another.

Claims

1. A method for use within a processor core of a device, said method comprising:

providing an input to receive a reference identifier from within the processor core;

providing an input to receive a program identifier associated with software stored in a system memory;

generating data that signifies receipt, or lack thereof, of a reference identifier and a program identifier having at least a specified measure of correspondence to one another; and

responding, substantially in hardware, to the data that signifies receipt, or lack thereof, including disabling an operating characteristic of the processor core unless the data indicates receipt of a program identifier and a reference identifier having at least a predetermined specified measure of correspondence to one another.

2. The method of claim 1 wherein responding comprises responding independently of the software stored in the system memory.

3. The method of claim 1 wherein responding comprises responding exclusively in hardware.

4. The method of claim 1 wherein responding to the data comprises receiving data through a data path separate from the address/data bus.

5. The method of claim 1 further comprising encrypting an identifier code stored in the processor core and generating the reference identifier in response to the encrypted identifier code.

6. The method of claim 5 wherein encrypting comprises encrypting the identifier code in response to an encryption strategy and a seed provided by the software stored in the system memory.

7. The method of claim 1 further comprising storing an identifier code in the processor core and providing indirect access to a form of the identifier code from outside the processor core.

8. The method of claim 7 wherein providing indirect access comprises providing indirect access to an encrypted form of the identifier code.

9. The method of claim 7 further comprising generating the program identifier in response to the form of the identifier code and storing the program identifier in the system memory.

10. The method of claim 8 further comprising determining the identifier code using decryption, generating the program identifier in response to the identifier code and an encryption strategy, and storing the program identifier in the software stored in the system memory.

11. The method of claim 6 further comprising preventing direct access to the identifier code from outside the processor core.

12. The method of claim 1 wherein responding comprises disabling an operating characteristic of the processor unless the data indicates receipt, within a specified duration from a specified event, of a program identifier and a reference identifier having at least a specified measure of correspondence to one another.

13. The method of claim 1 wherein the disabling is disabled if an emulator is active.

14. The method of claim 1 wherein disabling comprises disabling refresh of a watchdog timer unless the data indicates receipt, within a specified duration from a specified event, of a program identifier and a reference identifier having at least a specified measure of correspondence to one another.

15. The method of claim 14 wherein the watchdog timer is disabled if an emulator is active.

16. The method of claim 1 wherein the device is a cell phone.

17. A processor core comprising:

a comparator that receives a reference identifier from within the processor core and a program identifier associated with software stored in a system memory, and generates data that signifies receipt, or lack thereof, of a reference identifier and a program identifier having at least a specified measure of correspondence to one another; and

a disable system, responsive to the data indicative of a measure of correspondence, that generates a signal to disable an operating characteristic of the processor core unless the data indicates that there is at least a specified measure of correspondence between the program identifier and the reference identifier.

18. The processor core of claim 17 further comprising a register to store the reference identifier and wherein the comparator is operatively coupled to the register by a data path separate from a data path that couples the processor core and the system memory.

19. The processor core of claim 17 wherein the disable circuit receives the data through a data path separate from the data path that couples the processor core and the system memory.

20. The processor core of claim 18 wherein the disable circuit receives the data through a data path separate from the data path that couples the processor core and the system memory.

21. The processor core of claim 17 further comprising a digital circuit that encrypts an identifier code stored in the processor core and generates the reference identifier in response to the encrypted identifier code.

22. The processor core of claim 21 wherein the processor core provides indirect access to a form of the identifier code from outside the processor core.

23. The processor core of claim 21 wherein the processor core provides indirect access to an encrypted form of the identifier code.

24. The processor core of claim 21 wherein the processor core prevents direct access to the identifier code from outside the processor core.

25. The processor core of claim 17 wherein the disable system does not generate the signal to disable if an emulator is active.

26. The processor core of claim 17 wherein the disable system comprises a circuit to disable refresh of a watchdog timer.

27. The processor core of claim 26 wherein the watchdog timer is disabled if an emulator is active.

28. The processor core of claim 17 wherein the comparator is a digital circuit.

29. The processor core of claim 17 wherein the disable system is a circuit.

30. The processor core of claim 17 wherein the reference identifier is not accessible through an external terminal of the processor core.

31. A processor core comprising:

an input to receive a reference identifier from within the processor core;

an input to receive a program identifier associated with software stored in a system memory;

means for generating data that signifies receipt, or lack thereof, of a reference identifier and a program identifier having at least a specified measure of correspondence to one another; and

means for responding, substantially in hardware, to the data that signifies receipt, or lack thereof, the means for responding including means for disabling an operating characteristic of the processor core unless the data indicates receipt of a program identifier and a reference identifier having at least a specified measure of correspondence to one another.

32. An electronic device comprising:

a memory;

software that is stored in the memory and includes a program identifier;

a processor core coupled to the memory through a data path, the processor core including a comparator that receives the program identifier and a reference identifier, and in response thereto, generates a signal indicative of a measure of correspondence between the reference identifier and the program identifier, the processor core further including a disable system, responsive to the signal generated by the comparator and configured to disable an operating characteristic of the electronic device unless the signal indicates that there is at least a specified measure of correspondence between the reference identifier and the program identifier.

33. The electronic device of claim 32 wherein the comparator and the disable system are circuits.

34. The electronic device of claim 32 wherein the electronic device is a cell phone.

35. The device of claim 32 wherein the processor core further comprises a register to store the reference identifier and wherein the comparator is operatively coupled to the register by a data path separate from the data path that couples the processor core and the memory.

36. The device of claim 32 wherein the disable system receives the data through a data path separate from the data path that couples the processor core and the system memory.

37. The device of claim 32 wherein the processor core further comprises a digital circuit that encrypts an identifier code stored in the processor core and generates the reference identifier in response to the encrypted identifier code.

38. The device of claim 37 wherein the processor core provides indirect access to a form of the identifier code from outside the processor core.

39. The device of claim 37 wherein the processor core provides indirect access to an encrypted form of the identifier code.

40. The device of claim 37 wherein the processor core prevents direct access to the identifier code from outside the processor core.

41. The device of claim 32 wherein the disable system does not generate the signal to disable if an emulator is active.

42. The device of claim 32 wherein the disable system comprises a circuit to disable refresh of a watchdog timer.

43. The device of claim 42 wherein the disable system comprises a circuit to disable a watchdog timer if an emulator is active.

44. The device of claim 32 wherein the reference identifier is not accessible through an external terminal of the processor core.

45. A cell phone for mobile communication, the cell phone having a processor that includes a processor core and a memory, the processor core being coupled to the memory through a data path, the memory being usable to store software that includes a run-time program and an identifier associated with the software, wherein the improvement comprises:

a comparator, within the processor core, that receives a reference identifier from within the processor core and a program identifier associated with software stored in a system memory, and generates data that signifies receipt, or lack thereof, of a reference identifier and a program identifier having at least a specified measure of correspondence to one another; and

a disable system, within the processor core and responsive to the data indicative of a measure of correspondence, that generates a signal to disable an operating characteristic of the processor core unless the data indicates that there is at least a specified measure of correspondence between the program identifier and the reference identifier.