Programmable processor and method for partitioned group element selection operation
First Claim
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1. A programmable processor comprising:
- an instruction path;
a data path;
an external interface operable to receive data from an external source and communicate the received data over the data path;
a cache operable to retain data communicated between the external interface and the data path;
a register file operable to receive and store data from the data path and communicate the stored data to the data path; and
an execution unit coupled to the instruction path and the data path and operable to decode and execute instructions received from the instruction path, wherein in response to decoding a single instruction specifying a data selection operand and a first and a second register each having a register width, the first and second registers providing a plurality of data elements each having an elemental width smaller than the register width of the first and second registers, the data selection operand comprising a plurality of fields each selecting one of the plurality of data elements, the execution unit is operable to provide the data element selected by each field of the data selection operand to a predetermined position in a catenated result.
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Abstract
A programmable processor and method for improving the performance of processors by incorporating an execution unit operable to decode and execute single instructions specifying a data selection operand and a first and a second register providing a plurality of data elements, the data selection operand comprising a plurality of fields each selecting one of the plurality of data elements, the execution unit operable to provide the data element selected by each field of the data selection operand to a predetermined position in a catenated result.
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Citations
26 Claims
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1. A programmable processor comprising:
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an instruction path;
a data path;
an external interface operable to receive data from an external source and communicate the received data over the data path;
a cache operable to retain data communicated between the external interface and the data path;
a register file operable to receive and store data from the data path and communicate the stored data to the data path; and
an execution unit coupled to the instruction path and the data path and operable to decode and execute instructions received from the instruction path, wherein in response to decoding a single instruction specifying a data selection operand and a first and a second register each having a register width, the first and second registers providing a plurality of data elements each having an elemental width smaller than the register width of the first and second registers, the data selection operand comprising a plurality of fields each selecting one of the plurality of data elements, the execution unit is operable to provide the data element selected by each field of the data selection operand to a predetermined position in a catenated result. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12)
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13. A programmable processor comprising:
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an instruction path;
a data path;
an external interface operable to receive data from an external source and communicate the received data over the data path;
a cache operable to retain data communicated between the external interface and the data path;
a register file operable to receive and store data from the data path and communicate the stored data to the data path; and
an execution unit coupled to the instruction path and the data path and operable to decode and execute instructions received from the instruction path, wherein in response to decoding a single instruction specifying a data selection operand and a register having a register width, the register providing a plurality of data elements each having an elemental width smaller than the register width of the register, the data selection operand comprising a plurality of fields each selecting one of the plurality of data elements, the execution unit is operable to provide the data element selected by each field of the data selection operand to a predetermined position in a catenated result.
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14. A data processing system comprising:
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(a) a bus coupling components in the data processing system;
(b) an external memory coupled to the bus;
(c) a programmable microprocessor coupled to the bus and capable of operation independent of another host processor, the microprocessor comprising;
an instruction path;
a data path;
an external interface operable to receive data from an external source and communicate the received data over the data path;
a cache operable to retain data communicated between the external interface and the data path;
a register file operable to receive and store data from the data path and communicate the stored data to the data path; and
an execution unit coupled to the instruction path and the data path and operable to decode and execute instructions received from the instruction path, wherein in response to decoding a single instruction specifying a data selection operand and a first and a second register each having a register width, the first and second registers providing a plurality of data elements each having an elemental width smaller than the register width of the first and second registers, the data selection operand comprising a plurality of fields each selecting one of the plurality of data elements, the execution unit is operable to provide the data element selected by each field of the data selection operand to a predetermined position in a catenated result. - View Dependent Claims (15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25)
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26. A data processing system comprising:
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(a) a bus coupling components in the data processing system;
(b) an external memory coupled to the bus;
(c) a programmable microprocessor coupled to the bus and capable of operation independent of another host processor, the microprocessor comprising;
an instruction path;
a data path;
an external interface operable to receive data from an external source and communicate the received data over the data path;
a cache operable to retain data communicated between the external interface and the data path;
a register file operable to receive and store data from the data path and communicate the stored data to the data path; and
an execution unit coupled to the instruction path and the data path and operable to decode and execute instructions received from the instruction path, wherein in response to decoding a single instruction specifying a data selection operand and a register having a register width, the register providing a plurality of data elements each having an elemental width smaller than the register width of the register, the data selection operand comprising a plurality of fields each selecting one of the plurality of data elements, the execution unit is operable to provide the data element selected by each field of the data selection operand to a predetermined position in a catenated result.
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Specification